Topics tagged OOPS

Topic	Replies	Views	Activity
Understanding Automatic or Automatic Lifetime of Class objects - SV SystemVerilog SystemVerilog , assertion , class , OOPS , system-verilog-interface-generate	4	461	July 25, 2023
Question related to inheritance and classes SystemVerilog SystemVerilog , System-Verilog , OOPS , casting , Inheritance , cast	10	1638	October 15, 2022
Mailbox using inheritance SystemVerilog SystemVerilog , OOPS , inherited_classes , systemverilog-mailbox , systemverilog-class-event	2	826	April 12, 2022
Why base class can't be assigned to derived class? SystemVerilog SystemVerilog , OOPS , Inheritance	5	1241	October 3, 2020
OOPs based testbench of combinational adder SystemVerilog SystemVerilog , OOPS , Verification , layered-testbench	3	1439	August 23, 2019
OOPS: how to enforce that a function is implemented in derived class SystemVerilog SystemVerilog , OOPS	5	1455	September 29, 2018
Can we call a virtual method in base class using extended class handle/object? SystemVerilog SystemVerilog , OOPS	4	1545	September 6, 2018
Multiple Inheritance In system verilog SystemVerilog SystemVerilog , OOPS , Inheritance , Learning-System-Verilog , classes , inherited_classes	2	7075	August 27, 2018
OOPS - assigning base class SystemVerilog SystemVerilog , OOPS	5	3796	February 13, 2018
UVM class relations UVM UVM , OOPS	0	1108	February 11, 2018
OOPS and UVM UVM UVM , OOPS	2	1752	January 19, 2018
OOPS terminologies in SV SystemVerilog SystemVerilog , SV , OOPS	2	2386	January 7, 2018
How super.new and super.data functions? SystemVerilog SystemVerilog , OOPS , inherited_classes	1	1157	October 6, 2017
Dynamic memory consumption SystemVerilog SystemVerilog , OOPS	1	1135	September 21, 2017
Question on Non-Virtual Methods? SystemVerilog SystemVerilog , OOPS , non-virtual	2	1593	August 23, 2017
Mutiple test cases needs to be run sequentially in SV or UVM SystemVerilog SystemVerilog , OOPS	4	5278	March 24, 2017
Same property name in both base and derived class in System verilog SystemVerilog SystemVerilog , System-Verilog , SV , OOPS	1	3495	July 14, 2015
Create different handle of class in the macro based on number of times macro is called SystemVerilog OVM , SystemVerilog , OOPS	3	2274	April 2, 2015
Types are not Assignment compatible issue SystemVerilog SystemVerilog , OOPS	1	2739	May 8, 2014

Understanding Automatic or Automatic Lifetime of Class objects - SV

SystemVerilog

4

461

July 25, 2023

Question related to inheritance and classes

SystemVerilog

SystemVerilog , System-Verilog , OOPS , casting , Inheritance , cast

10

1638

October 15, 2022

Mailbox using inheritance

SystemVerilog

SystemVerilog , OOPS , inherited_classes , systemverilog-mailbox , systemverilog-class-event

2

826

April 12, 2022

Why base class can't be assigned to derived class?

SystemVerilog

SystemVerilog , OOPS , Inheritance

5

1241

October 3, 2020

OOPs based testbench of combinational adder

SystemVerilog

SystemVerilog , OOPS , Verification , layered-testbench

3

1439

August 23, 2019

OOPS: how to enforce that a function is implemented in derived class

SystemVerilog

SystemVerilog , OOPS

5

1455

September 29, 2018

Can we call a virtual method in base class using extended class handle/object?

SystemVerilog

SystemVerilog , OOPS

4

1545

September 6, 2018

Multiple Inheritance In system verilog

SystemVerilog

SystemVerilog , OOPS , Inheritance , Learning-System-Verilog , classes , inherited_classes

2

7075

August 27, 2018

OOPS - assigning base class

SystemVerilog

SystemVerilog , OOPS

5

3796

February 13, 2018

UVM class relations

UVM

UVM , OOPS

0

1108

February 11, 2018

OOPS and UVM

UVM

UVM , OOPS

2

1752

January 19, 2018

OOPS terminologies in SV

SystemVerilog

SystemVerilog , SV , OOPS

2

2386

January 7, 2018

How super.new and super.data functions?

SystemVerilog

SystemVerilog , OOPS , inherited_classes

1

1157

October 6, 2017

Dynamic memory consumption

SystemVerilog

SystemVerilog , OOPS

1

1135

September 21, 2017

Question on Non-Virtual Methods?

SystemVerilog

SystemVerilog , OOPS , non-virtual

2

1593

August 23, 2017

Mutiple test cases needs to be run sequentially in SV or UVM

SystemVerilog

SystemVerilog , OOPS

4

5278

March 24, 2017

Same property name in both base and derived class in System verilog

SystemVerilog

SystemVerilog , System-Verilog , SV , OOPS

1

3495

July 14, 2015

Create different handle of class in the macro based on number of times macro is called

SystemVerilog

OVM , SystemVerilog , OOPS

3

2274

April 2, 2015

Types are not Assignment compatible issue

SystemVerilog

SystemVerilog , OOPS

1

2739

May 8, 2014