Topics tagged Inheritance

Topic	Replies	Views	Activity
Best Practice for Unit Tests Extending Chip-Level Tests UVM SystemVerilog , Inheritance	1	276	April 6, 2024
Extending parameterized classes SystemVerilog Virtual-methods , Inheritance , ParameterizedClass	4	611	January 5, 2024
Systemverilog inheritance question SystemVerilog SystemVerilog , sequence , Inheritance	4	675	January 24, 2023
Can we use factory type override for a sub-class that has extra methods? UVM UVM , factory , Inheritance	2	605	January 14, 2023
Getting class derivatives names from factory UVM UVM , Polymorphism , factory , OOP , Inheritance	3	710	January 8, 2023
Question related to inheritance and classes SystemVerilog SystemVerilog , System-Verilog , OOPS , casting , Inheritance , cast	10	1738	October 15, 2022
Member variable to be only inherited by immediate child SystemVerilog SystemVerilog , Inheritance	8	1122	July 5, 2021
Super.Super() call alternative system verlilog SystemVerilog SystemVerilog , Inheritance	1	922	June 29, 2021
Base and Derived Class Randomization SystemVerilog SystemVerilog , Inheritance , randomization	5	1848	February 14, 2021
Base class override in UVM testbench UVM SystemVerilog , UVM , Inheritance , factory-overrides , class-override , Base-test	5	2664	December 14, 2020
Why base class can't be assigned to derived class? SystemVerilog SystemVerilog , OOPS , Inheritance	5	1267	October 3, 2020
Inheritance/ Same variable declared in derived class as parent class SystemVerilog SystemVerilog , Inheritance	1	827	September 3, 2020
What is the difference between a base class and a parent class in UVM UVM UVM , Inheritance , OOP-polymorphism-MoveOperation-UVM	4	2348	May 26, 2020
What is the difference between Super and Virtual keywords when accessing methods in a Base Class? SystemVerilog SystemVerilog , Virtual-methods , Inheritance , Polymorhphism	1	2079	March 31, 2020
Inheritance example SystemVerilog SystemVerilog , Inheritance	1	1218	February 21, 2020
What is multiple and multi-layer inheritance in system verilog SystemVerilog SystemVerilog , Inheritance	1	1589	December 17, 2019
Inheritance case SystemVerilog SystemVerilog , Inheritance	2	1046	October 21, 2018
Multiple Inheritance In system verilog SystemVerilog SystemVerilog , OOPS , Inheritance , Learning-System-Verilog , classes , inherited_classes	2	7219	August 27, 2018
How can I use parent class's member variable in systemverilog? SystemVerilog SystemVerilog , Inheritance	2	6562	August 8, 2018
Multiple inheritence in SV SystemVerilog SystemVerilog , SV , Inheritance	2	2456	January 2, 2018
Question on Inheritance in SV SystemVerilog SystemVerilog , Inheritance	13	3427	December 7, 2017
Partial override of a class OVM OVM , function , class , override , Inheritance	4	2228	October 23, 2017
Class member variable re-declaration SystemVerilog SystemVerilog , Inheritance , classes	4	1766	July 12, 2017
Inheritance overridden member - memory allocation issue SystemVerilog SystemVerilog , Inheritance	2	1529	October 14, 2016
Base class handle for extended class is not working in SystemVerilog SystemVerilog SystemVerilog , Inheritance , class-handle , instantiation-vs-inheritance	2	2932	August 18, 2016
Difference between inheritance and polymorphism SystemVerilog SystemVerilog , Inheritance , Polymorhphism	4	10594	August 12, 2016
Task overriding in a sub class SystemVerilog SystemVerilog , Polymorphism , Inheritance	4	6686	May 17, 2016
Problem in casting and super SystemVerilog SystemVerilog , Inheritance	1	1274	May 12, 2016
Can derived class object call base class (virtual/non-virtual) function? SystemVerilog SystemVerilog , Polymorphism , Virtual-methods , Inheritance , Nonvirtual-methods	3	4983	September 22, 2015
Inheritance Vs Composition in System Verilog world SystemVerilog SystemVerilog , System-Verilog , OOP , Composition , Inheritance	0	3356	September 10, 2014

Best Practice for Unit Tests Extending Chip-Level Tests

UVM

SystemVerilog , Inheritance

1

276

April 6, 2024

Extending parameterized classes

SystemVerilog

Virtual-methods , Inheritance , ParameterizedClass

4

611

January 5, 2024

Systemverilog inheritance question

SystemVerilog

SystemVerilog , sequence , Inheritance

4

675

January 24, 2023

Can we use factory type override for a sub-class that has extra methods?

UVM

UVM , factory , Inheritance

2

605

January 14, 2023

Getting class derivatives names from factory

UVM

UVM , Polymorphism , factory , OOP , Inheritance

3

710

January 8, 2023

Question related to inheritance and classes

SystemVerilog

SystemVerilog , System-Verilog , OOPS , casting , Inheritance , cast

10

1738

October 15, 2022

Member variable to be only inherited by immediate child

SystemVerilog

SystemVerilog , Inheritance

8

1122

July 5, 2021

Super.Super() call alternative system verlilog

SystemVerilog

SystemVerilog , Inheritance

1

922

June 29, 2021

Base and Derived Class Randomization

SystemVerilog

SystemVerilog , Inheritance , randomization

5

1848

February 14, 2021

Base class override in UVM testbench

UVM

SystemVerilog , UVM , Inheritance , factory-overrides , class-override , Base-test

5

2664

December 14, 2020

Why base class can't be assigned to derived class?

SystemVerilog

SystemVerilog , OOPS , Inheritance

5

1267

October 3, 2020

Inheritance/ Same variable declared in derived class as parent class

SystemVerilog

SystemVerilog , Inheritance

1

827

September 3, 2020

What is the difference between a base class and a parent class in UVM

UVM

UVM , Inheritance , OOP-polymorphism-MoveOperation-UVM

4

2348

May 26, 2020

What is the difference between Super and Virtual keywords when accessing methods in a Base Class?

SystemVerilog

SystemVerilog , Virtual-methods , Inheritance , Polymorhphism

1

2079

March 31, 2020

Inheritance example

SystemVerilog

SystemVerilog , Inheritance

1

1218

February 21, 2020

What is multiple and multi-layer inheritance in system verilog

SystemVerilog

SystemVerilog , Inheritance

1

1589

December 17, 2019

Inheritance case

SystemVerilog

SystemVerilog , Inheritance

2

1046

October 21, 2018

Multiple Inheritance In system verilog

SystemVerilog

SystemVerilog , OOPS , Inheritance , Learning-System-Verilog , classes , inherited_classes

2

7219

August 27, 2018

How can I use parent class's member variable in systemverilog?

SystemVerilog

SystemVerilog , Inheritance

2

6562

August 8, 2018

Multiple inheritence in SV

SystemVerilog

SystemVerilog , SV , Inheritance

2

2456

January 2, 2018

Question on Inheritance in SV

SystemVerilog

SystemVerilog , Inheritance

13

3427

December 7, 2017

Partial override of a class

OVM

OVM , function , class , override , Inheritance

4

2228

October 23, 2017

Class member variable re-declaration

SystemVerilog

SystemVerilog , Inheritance , classes

4

1766

July 12, 2017

Inheritance overridden member - memory allocation issue

SystemVerilog

SystemVerilog , Inheritance

2

1529

October 14, 2016

Base class handle for extended class is not working in SystemVerilog

SystemVerilog

SystemVerilog , Inheritance , class-handle , instantiation-vs-inheritance

2

2932

August 18, 2016

Difference between inheritance and polymorphism

SystemVerilog

SystemVerilog , Inheritance , Polymorhphism

4

10594

August 12, 2016

Task overriding in a sub class

SystemVerilog

SystemVerilog , Polymorphism , Inheritance

4

6686

May 17, 2016

Problem in casting and super

SystemVerilog

SystemVerilog , Inheritance

1

1274

May 12, 2016

Can derived class object call base class (virtual/non-virtual) function?

SystemVerilog

SystemVerilog , Polymorphism , Virtual-methods , Inheritance , Nonvirtual-methods

3

4983

September 22, 2015

Inheritance Vs Composition in System Verilog world

SystemVerilog

SystemVerilog , System-Verilog , OOP , Composition , Inheritance

0

3356

September 10, 2014