Inheritance case

SystemVerilog
,
1

Please look at the following case.
The base class has func1 and func2. func2 calls func2.
The derived class overrides func1.

An instance of derived class is created and func2 is called using derived class variable.
The output produced is: func1 in base

It is not clear to me how func1 is called from base class in this case.
I am not contesting the results but I would like to know how func2 is called from derived class but func1 from base class

class base ;

task func1();
  $display ("func1 in base");
endtask

task func2();
  func1(); 
endtask
  
endclass  
  
class Derivedbase extends base ;
  
task func1();
  $display ("func1 in derived");
endtask

endclass
  
module test;
  Derivedbase db = new();
  
initial
  db.func2();

endmodule
2

In reply to verif_learner:

Hi I see this is as a classic example where virtual keyword makes the difference. If virtual keyword is added in the base class then you would see the code calling derived f1 else it would still call the func1 in base…

Siva

3

In reply to verif_learner:

You do seem to be contesting the results. I though you already discussed this extensively here.