Task overriding in a sub class

SystemVerilog
, ,
1

Hi

I am trying to overwrite a task in the subclass (these are sequences) and when executing it , iam seeing that the original task in base class is only getting executed and not the new overridden task

class baseclass;

task body();
run_the_sim();
endtask:body;

virtual task run_the_sim(int a);
a = a+3;
$display("a val %d",a );
endtask

endclass: baseclass

class subclass extends baseclass;

task body();
super.body();
endtask : body

task run_the_sim(int a);
a = a+10;
$display("a val %d",a );
endtask

endclass

in the test, i call the seq like this

subclass subclass_seq;
`ovm_do_with (subclass_seq,
{
a == 10;
}
)

I am seeing the old task getting executed? can you pls help

Thank you!

2

In reply to theketi:
Your subclass class looks fine to me. The most likely cause is that you somehow constructed the base instead of the subclass.

3

In reply to dave_59:

I see.

I also have this in my subclass (extended class)

function new (string name = “”);
super.new(name);
endfunction : new

task body();
  $display("Extended subclass body task ");
  super.body();
  $display("Extended subclass body has been executed");
endtask:body

And i do see the statements inside the body task being executed. I can see the prints
However just the new task is not being executed.

4

In reply to theketi:
Are you sure run_the_sim is declared as virtual in the baseclass? I have no other ideas for you.

5

I guess that was the issue , i didnt compile after some changes and it didnt pick virtual. Thanks Dave!