What is multiple and multi-layer inheritance in system verilog

SystemVerilog
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1

what is multiple and multi-layer inheritance in system verilog??

-according to SV-LRM 8.13 The mechanism provided by SystemVerilog is called single inheritance, that is, each class is derived from a single base class.

class parent_class;
  bit [31:0] addr;
  function display();
	  $display(" parent class = %d", addr);
  endfunction
endclass

class child_class extends parent_class;
  bit [31:0] data;
  function display();
	  $display(" child class11 = %d", data);
  endfunction
endclass

class sec_child_class extends child_class;
  bit [31:0] ctrl;
  function display();
	  $display(" sec_child class = %d, child class =%d", ctrl, data);
  endfunction

endclass

module inheritence;
    sec_child_class c = new();
    child_class cc =new();
  initial begin
    //sec_child_class c = new();
    c.addr = 10;
    c.data = 20;
    c.ctrl = 30;
    cc.display();
    c.display();
    //$display("Value of addr = %0d data = %0d ctrl = %d",c.addr,c.data, c.ctrl);
  end
2

In reply to muku_383:

The multiple inheritance concept is not supported in systemverilog OOPS.
Single class derived from multiple base class is called as multiple inheritance.

Example::

class a;
…
endclass

class b;
…
enclass

class c extends a,b;
…
endclass