Inheritance/ Same variable declared in derived class as parent class

SystemVerilog
,
1

Hi,

I have a doubt in the following implementation:

class parent_class;
  bit [31:0] addr;
  bit [31:0] data;
  function new();
    addr= 'hffff;
    data = 'h5555;
  endfunction
  
  task display();
    $display("Base Addr = %h and data %h",addr,data);
  endtask
endclass
 
class child_class extends parent_class;
  bit [31:0] data;
  bit [31:0] addr;
 
   function new();  
    addr='h8888;
    data = 'h1234;
  endfunction
  
  task display();
    super.display();
    $display("Ext Data = %h, addr = %h", addr,data);
  endtask
 
endclass
 
module inheritence;
  initial begin
    child_class c;
    parent_class b;
    b =new();
    c= new();
    $display("%p", c);
    c.display();
  end
endmodule

Output:
‘{super:’{addr:'hffff, data:'h5555}, data:'h1234, addr:'h8888}
Base Addr = 0000ffff and data 00005555
Ext Data = 00008888, addr = 00001234

Why does the addr and data values from the base class used in super.display() which is called from extended class?

Whereas if I overwrite the value of addr and data in the extended class, without explicitly declaring addr and data, then extended class values are printed using super.display() function. The code is as follows:

class parent_class;
  bit [31:0] addr;
  bit [31:0] data;
  function new();
    addr= 'hffff;
    data = 'h5555;
  endfunction
  
  task display();
    $display("Base Addr = %h and data %h",addr,data);
  endtask
endclass
 
class child_class extends parent_class;
 
   function new();  
    addr='h8888;
    data = 'h1234;
  endfunction
  
  task display();
    super.display();
    $display("Ext Data = %h, addr = %h", addr,data);
  endtask
 
endclass
 
module inheritence;
  initial begin
    child_class c;
    parent_class b;
    b =new();
    c= new();
    $display("%p", c);
    c.display();
  end
endmodule

Output:
‘{super:’{addr:'h8888, data:'h1234}}
Base Addr = 00008888 and data 00001234
Ext Data = 00008888, addr = 00001234

Thanks,
Sakshi

2

In reply to ssakshi:

See How can I use parent class's member variable in systemverilog? | Verification Academy

Use of “super” with %p seems to be specific to one tool.