Base class override in UVM testbench

UVM
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1

Hi all,

I have a testbench with the following testcase heirarchy:

class base_test extends uvm_test;
…
endclass

class test_A extends base_test;
…
endclass

class test_1 extends test_A; … endclass
class test_2 extends test_A; … endclass
class test_3 extends test_A; … endclass

New testcase:
class test_B extends base_test’
…
endclass

I want to override the middle base test class(test_A) with another testcase(test_B).
I don’t want to change the child classes as they’re having some constraints and could be re-used for my new base testcase(test_B).

What is the recommended way to do this?

Appreciate everyone’s help.

Thanks

2

In reply to sv_uvm_49:
I think as long as you maintain the integrity (i.e, methods or properties which you are accessing in child class of test_A are also available in test_B) then you can use override macros of uvm.

3

Hi tez,
Thanks for your reply.

Could you be a little more specific on where should I do the factory override?

4

In reply to sv_uvm_49:

Hi tez,
Thanks for your reply.
Could you be a little more specific on where should I do the factory override?

Hi,
I think we need use the factory override inside the base_test build_phase() such that test_A is replaced by test_B (you need to have the same methods with its arguments of test_A)

5

In reply to avpchandra:

You cannot override a class in the middle chain of inheritance.

One option is to rename test_A to test_A_base, then insert a new class into the chain called test_A that is extended from test_A_base.

If that doesn’t work for you, you’ll have to explain more about what you’re trying to accomplish. There might be other ways of organizing your classes. For example, see the links on this post.

6

In reply to dave_59:
Agreed dave_59. sv_uvm_49, if you aren’t having the handle/instance of base_obj in TB then overriding won’t help straight away. As dave_59 suggested, we can make a in-between class or other ways available in the link provided by dave_59.