Topics tagged sequence

Topic	Replies	Views	Activity
Uvm_do_on running sequence on multiple sequencers directly UVM sequence , uvm_sequence , InterviewQuestions	3	50	February 13, 2025
Calling two sequencer from one sequence UVM sequencer , sequence	3	93	December 27, 2024
Is there a build-in API to get the obj of seq in the seqr which the seq is running? UVM sequence	2	105	September 25, 2024
Sequence task get stuck in wait_for_grant() UVM UVM , sequence , wait_for_grant	7	732	December 14, 2023
Assertion SystemVerilog SystemVerilog , assertion , Package , sequence , systemverilogassertionSVA	2	400	November 17, 2023
Sequence Library UVM UVM , sequence , sequence-library , configurability	3	638	September 8, 2023
Sequence not getting config object from config_db UVM UVM , sequence , uvm-register-sequences , uvm-config_db	7	682	July 19, 2023
Can we start one sequence onto the driver while it is driving another sequence? UVM UVM , sequence , UVM-monitor-sequencer-Agent-TLM_FIFO , UVM-sequence-sequencer-nested_sequence-transaction	2	549	June 9, 2023
Can I send parent sequence item and child sequence item at the same time to the Driver? UVM UVM , sequence	1	640	May 11, 2023
How to mask the write data and read data in a register in UVM sequence UVM UVM , registers , sequence , access-register-in-uvm-monitor , registers_testing , register-masking	1	742	February 21, 2023
Error on sequencer - send_request failed to cast sequence item UVM UVM , sequence , casting , uvm_fatal	9	2783	February 1, 2023
Issue when using uvm_reg update method: "Accessing non-static members of a null object is not allowed" UVM UVM , sequence , uvm_reg	2	905	January 26, 2023
Systemverilog inheritance question SystemVerilog SystemVerilog , sequence , Inheritance	4	664	January 24, 2023
How can one write a UVM sequence for cache eviction? Lets suppose main memory is 4GB. 64KB Cache, 4 way associative, 64B cache line. Any ideas would be appreciated UVM SystemVerilog , UVM , sequence , delay-uvm_components	0	485	January 14, 2023
What is the use of sequence overrides UVM UVM , override , sequence , set_type_override , uvm_set_inst_override	0	676	August 29, 2022
How sequences is start? UVM UVM , sequence , uvm-sequence-test	1	556	June 26, 2022
Uvm sequence for registers test UVM UVM , sequence , regmodel	2	820	June 20, 2022
UVM Constrains inside a sequence are ignored UVM UVM , sequence , constraint-randomization , sequence-item , systemverilog-uvm	5	1067	June 13, 2022
SVA Sequence Subtleties (Sequence fusion / Sequence concatenation) SystemVerilog SystemVerilog , assertion , sequence , verifcation , Assertion-property	4	947	May 25, 2022
I don't understand these sentences about concurrent assertion and simulation event SystemVerilog SystemVerilog , assertion , sequence , scheduling	3	672	April 27, 2022
Reactive agent for memory storage UVM UVM , sequence , reactive-agent	11	3652	March 18, 2022
Get_response function in sequence does not get unblocked after put_response UVM UVM , sequence , get_response , driver , systemverilog-uvm	2	1111	February 3, 2022
Passing queue through sequence_item UVM UVM , sequencer , sequence , driver , Queues , sequence-item	2	1295	January 22, 2022
SEQUENCE ITEM UVM UVM , sequence	1	624	December 6, 2021
Multiple packet in sequence and how to send those packet to specific seqr? UVM UVM , sequence	0	815	October 22, 2021
Sequence in go-to reptition and non-consecutive repetition SystemVerilog SystemVerilog , SVA , sequence	1	732	October 20, 2021
Address generation for use in sequences UVM UVM , sequence , address-generation	0	625	October 13, 2021
Default sequence in UVM UVM UVM , default_sequence , sequence	3	6975	October 13, 2021
Simulation changing with respect to Sequence name UVM UVM , sequence , create	3	818	August 26, 2021
Sequence to that respond to done signal UVM UVM , sequence , get_response , Response-API , sequence-body	14	1928	August 23, 2021