Hey all, I hope you’re doing great.
Im trying o verify my DUT registers, I add a regmodel in the TB. I wanted to make sure if some of my readings are correct or not.
to test rw register access; Are uvm_reg_bit_bash_seq and uvm_reg_single_bit_bash_seq what im looking for ?
In reply to abdelaali_21:
If you want to access all the registers in register map, use uvm_reg_bit_bash_seq, for single register access use uvm_reg_single_bit_bash_seq.
- uvm_reg_single_bit_bash_seq - Verify the implementation of a single register
- uvm_reg_bit_bash_seq - Verify the implementation of all registers in a block by
executing the uvm_reg_single_bit_bash_seq sequence on it.
In reply to Alokpati:
Did you mean register rw acces by " implementation" ? if not what sequence should I use to test register access ?