Topics tagged uvm

Topic	Replies	Views	Activity
Has anyone implemented a Write 1 only self-clearing policy for a uvm_reg_field? UVM UVM , uvm_reg , Access-Policy	2	83	October 30, 2024
UVM RAL: Check on read issue UVM Mirrored-values-and-desired-values-in-UVM-RAL , uvm_reg , uvm-ral	0	155	September 23, 2024
How to check the register is implemented in UVM RAL with the address UVM UVM , RAL , uvm_reg	1	158	September 3, 2024
[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique UVM SystemVerilog , UVM , uvm_reg , RAL-UVM	1	1310	April 16, 2024
Mirrored Value is not getting updated for second reg model's write/read calls UVM SystemVerilog , UVM , uvm_reg , uvm-ral , mirrored-value , Calling-predict-for-registers	0	480	September 4, 2023
Write access to RO register updates mirror value to 0 UVM UVM , uvm_reg	0	275	April 6, 2023
Issue when using uvm_reg update method: "Accessing non-static members of a null object is not allowed" UVM UVM , sequence , uvm_reg	2	927	January 26, 2023
Is there a way I can disable checking for a specific register in a register map defined using uvm_reg? UVM UVM , uvm_reg_map , uvm_reg	2	1624	October 5, 2022
Problem with constructing UART reg model UVM SystemVerilog , UVM , uvm_reg , UART	0	446	June 11, 2022
RAL back door access UVM UVM , uvm_reg , adapter-register , RAL-efficient , UVM-RAL-BACKDOOR , RAL-UVM-PREDICTOR	2	1478	May 25, 2022
Have you ever used the Factory to override by type/name a uvm_reg/uvm_field? UVM UVM , uvm_reg , shadow	2	585	April 17, 2022
How to access fields in encrypted UVM reg model UVM UVM , uvm_reg , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	2	637	February 11, 2022
How to know backdoor access can't use or not? UVM UVM , uvm_reg	8	1728	January 19, 2022
Using uvm_reg instead of uvm_mem to create memory in ral model, but it's consume too much tool memory and causing the error? UVM UVM , uvm_reg	2	689	January 13, 2022
Uvm_reg_field Individual Byte Access Works in UVM 1.2 but not in UVM IEEE 1800.2-2017 UVM UVM , uvm_reg , UVM_reg_field , IEEE , individually_accessible , supports_byte_enable	2	1317	January 8, 2021
Uvm_reg protocol level error/pio hole err injection UVM UVM , uvm_reg	0	791	April 3, 2020
Uvm_reg_file UVM UVM , uvm_reg , uvm_reg_file	1	1299	February 13, 2020
Get_mirrored_value() mismatch UVM UVM , uvm_reg , mirror , get_mirrored_value	4	3042	January 9, 2020
UVM RAL implementation methodology for large designs UVM UVM , uvm_reg , uvm-ral	0	1203	September 6, 2019
X in uvm_reg transactions UVM UVM , uvm_reg_adapter , uvm_reg , uvm-ral	7	2215	July 4, 2019
UVM reg field access via name UVM UVM , uvm_reg , UVM_reg_field , get_field_by_name , get_parent	5	6922	June 19, 2019
Multiple agents accessing a single uvm_reg_block UVM UVM , sequencer-agents , uvm_reg , adapter-register , multimaster	2	1556	November 3, 2018
Uvm reg predict issue UVM UVM , predict , uvm_reg , m_mirrored	7	14938	October 15, 2018
UVM Reg with indirect address map? UVM UVM , uvm_reg , indirect_addressing	1	1523	July 13, 2018
UVM_REG_BLOCK from UVM_REG UVM UVM , RAL , uvm_reg	1	2993	May 22, 2018
How to do uvm built in bit-bash sequence /read-write on Indirect addressed registers? UVM UVM , uvm_reg , Advanced-UVM-Register , uvm_reg_bit_bash_seq , indirect_addressing	0	1786	May 14, 2017
How to print variable of type uvm_reg? UVM UVM , uvm_reg , uvm-ral	2	6109	November 23, 2016
UVM RAL Related UVM UVM , uvm_reg_adapter , uvm_reg , uvm_reg_predictor	1	1598	November 8, 2016
How to support multiple register maps in a SOC system for a block with only one register map? UVM UVM , uvm_reg , UVM-reuse	6	11740	November 1, 2016
Uvm_reg::read mirrored value immediately overwritten by subseqent uvm_reg::write UVM UVM , uvm_reg , mirrored-value , immediately-overrides	0	1384	August 5, 2016