UVM Reg with indirect address map?

UVM
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Hi. I’ve been using UVM for a few years and UVM Reg for the last few months. I have set up a working verification environment using a generated register block RTL and generated UVM Reg model. I have working tests using .write/.read/.etc methods and also the standard uvm_reg_hw_reset_seq, uvm_reg_bit_bash_seq, and uvm_reg_access_seq. However, I’m now adding another register block that doesn’t directly connect to the system bus. Instead, there’s data, address, and control registers on the main bus that kick off transactions to the new register block on a separate, local bus (all Wishbone, FYI). I don’t know how to set up the UVM Reg classes and methods to access this cleanly without resorting to brute-force tasks that don’t take advantage of the UVM reg model for the block.

Any pointers to how to do this or general info on using indirect access in UVM Reg?

Thanks,

David

2

Hey David,
you could add a separate agent for the local bus. This agent should provide write/read tasks which internally follow the register access protocol through the system bus.
you can still use uvm reg for the new register block by connecting to the sequencer of the new agent (write custom reg_adapter)