My design demands two reg models, and I cannot update the mirrored value for uvm_reg::write() calls ONLY for the second reg model.
I see that the design is working as expected, and the original register values are getting updated. The mirrored values are not getting updated because we are not calling the predict() function.
TB details: (names are made up)
I have one monitor (x_mon), one analysis port inside x_mon (x_ap), two reg models (x_ral[2]), one reg adapter (x_reg_adap), two reg predictors (x_predictor[2]), and other uvm modules as needed.
Connections I have:
(1) (x_env) reg models are created with build() and lock_model()
x_ral[0..1].build();
x_ral[0..1].lock_model();
(2) (x_env)
x_predictor[0..1].map = x_ral[0..1].default_map;
x_predictor[0..1].adapter = x_reg_adap;
(3) (x_env)
x_mon.x_ap.connect(x_predictor[0..1].bus_in);
(4) (x_test)
x_ral[0].x_reg.write();// -> works fine
x_ral[1].x_reg.write();// -> does not work.
How I think updating the mirrored value works:
For a read() call → read response comes to the monitor from the design via IFC → monitor has its Analysis Port connected to predictor’s bus_in → predictor calls predict() → mirrored value gets updated.
For a write() call → it internally calls set(), which sends the txn to the design and also updates the mirrored value.
Question 1) Can somebody please point out if I need to do anything while I am writing for the same register of the second register model? As the first register model works fine, I am confused about what I am missing here.
Question 2) If I do x_ral[1].x_reg.get_mirrored_value(), I am getting the mirrored value of x_ral[0].x_reg. Am I missing anything here?