RAL back door access

UVM
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1

Hi,
I created Register Model for DMA(direct memory access) and added HDL paths using add_hdl_path_slice for registers and add_hdl_path for the entire register model
The code is compiled free and when I do front door access using(WRITE and READ) methods it is happening but when I do Backdoor access(POKE and PEEK) I am not getting the output it is showing some errors as below.

UVM_ERROR /dv/p4Cusers01nd/dvcmin_noida_main_rc_xcelium_102020_180012_linux/uvm/src/uvm12ml/distrib/src/dpi/uvm_hdl_inca.c(568) @ 15: reporter [UVM/DPI/NOBJ2] name tbench_top.DUT.ctrl cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR /dv/p4Cusers01nd/dvcmin_noida_main_rc_xcelium_102020_180012_linux/uvm/src/uvm12ml/distrib/src/dpi/uvm_hdl_inca.c(568) @ 15: reporter [UVM/DPI/NOBJ2] name tbench_top.DUT.io_addr cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR /dv/p4Cusers01nd/dvcmin_noida_main_rc_xcelium_102020_180012_linux/uvm/src/uvm12ml/distrib/src/dpi/uvm_hdl_inca.c(568) @ 15: reporter [UVM/DPI/NOBJ2] name tbench_top.DUT.mem_addr cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)

I am attaching the link to the code that i have written please check and help me out

LINK: Error

Thanks a lot in advance
Harshavardhan

2

In reply to Harsha vardhan:

The names of your HDL paths are incorrect. For example, the ‘ctrl’ register is named ‘control’ in the RTL, not ‘ctrl’. The same issue affects the other registers as well.

If you fix the HDL register path names, you will not get these errors.

3

In reply to cgales:
Thank You so much. It worked!!