Hello,
I was wondering if are there any resources (papers, blogs, posts) about methodologies to implement UVM RAL for “large” designs (>100K registers and 500K rams)? I tried to do some research online but most of the results never cover “large” designs.
I have experience using RAL and doing some customisations to make it work in a particular environment (callbacks, maps, defining specialised registers, sequences) but most of them were “little” (1K regs and 100 rams)
I’m interested aspects such as:
- Reg model re-usability and portability at sub-system and system level environments
- Performance: How heavy is the register model, since having this much registers may have a huge performance penalty over simulations
- Dynamic reconfiguration (I know in 1.2 once your model is locked not much can be done)
- RAM modelling in RAL (since it the uvm_mem is different from uvm_reg)
- Register Model Partitioning at block level
- Register Model limitations on real projects usage
Any material or hints on these topics is really appreciated
Apologies for the broad question but I consider this forum one of the best (if not the best) resource to discuss with verification experts
Thanks
-Ronald