Topics tagged RAL

Topic	Replies	Views	Activity
Implementing Outstanding AXI transactions using RAL UVM UVM , RAL , uvm-ral	1	30	December 19, 2024
RAL Coverage , Multiple Instance issue UVM RAL	2	34	November 26, 2024
Factory in RAL , create vs new UVM RAL	1	49	November 19, 2024
Mirrored value in frontdoor and backdoor UVM RAL	1	36	November 19, 2024
I want to apply RAL for UART Interface that has TX signal only UVM RAL	1	39	November 11, 2024
Register abstraction layer , where can i define the offset of the registers? UVM RAL	1	38	November 4, 2024
Requirement of both local_map & map UVM RAL , uvm-register-model	2	35	October 30, 2024
Advantage of calling set() over write() UVM UVM , RAL , uvm-ral	2	91	October 27, 2024
RESET Assertion with out clock dependency SystemVerilog OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog	1	89	October 18, 2024
Handling multiple RAL request simultaneously UVM UVM , RAL	2	118	September 26, 2024
Can't explain different behavior of 2 RAL registers with W1C fields UVM RAL	1	63	September 20, 2024
How to Selectively skip STS ( RO ) registers in bit_bash UVM UVM , RAL , uvm_reg_bit_bash	0	63	September 19, 2024
How to check the register is implemented in UVM RAL with the address UVM UVM , RAL , uvm_reg	1	106	September 3, 2024
Testing of Read/Write register through RAL when bug is there UVM UVM , RAL	1	108	August 22, 2024
How to get Backdoor Access for Memory? UVM RAL	0	104	August 8, 2024
Proper reg_map has not picked up UVM RAL	5	146	July 4, 2024
UVM register model UVM RAL , uvm-ral	0	108	July 1, 2024
RAL Register access UVM RAL	3	261	May 16, 2024
Skipping a register field from comparison with RAL UVM RAL , uvm_ral , RAL-UVM	10	459	May 15, 2024
Macro to read register fields using RAL Coverage UVM , Coverage , assertion , RAL , System-Verilog	1	286	March 26, 2024
How to use get_full_hdl_path for the register UVM RAL	0	311	March 15, 2024
RAL Backdoor access, set hdl paths UVM UVM , RAL	1	273	February 29, 2024
Question related to RAL methods SystemVerilog UVM , RAL , uvm_ral , RAL-UVM	0	262	February 26, 2024
How to access UVM_MEM using the .write method UVM UVM , RAL , uvm_mem	2	400	February 25, 2024
UVM RAL Memory - Sampling after read/write operation UVM SystemVerilog , Coverage , RAL , uvm_mem , Sampling	0	427	February 3, 2024
My question is how to verify “R0” (Read only) registers through backdoor or front door mechanism ? In frontdoor usually we do masking of RO registers to not to write .If RO register is designed with bug with RW type how to verify this issue without write UVM RAL	1	348	January 23, 2024
In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor? UVM UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	0	304	December 29, 2023
Access (to W/R) 2 Specific fields in a 32-bit register UVM RAL , uvm-ral , Systemverilog-UVM-RAL	1	295	December 27, 2023
RAL Integration UVM UVM , RAL , APB , vip-intergrate , register_model	0	388	December 11, 2023
I had an issue regarding RAL, i am unable to create a map which should contains maps of different invidual registers UVM UVM , RAL , RAL-UVM	0	320	December 6, 2023

Implementing Outstanding AXI transactions using RAL

UVM

UVM , RAL , uvm-ral

1

30

December 19, 2024

RAL Coverage , Multiple Instance issue

UVM

RAL

2

34

November 26, 2024

Factory in RAL , create vs new

UVM

RAL

1

49

November 19, 2024

Mirrored value in frontdoor and backdoor

UVM

RAL

1

36

November 19, 2024

I want to apply RAL for UART Interface that has TX signal only

UVM

RAL

1

39

November 11, 2024

Register abstraction layer , where can i define the offset of the registers?

UVM

RAL

1

38

November 4, 2024

Requirement of both local_map & map

UVM

RAL , uvm-register-model

2

35

October 30, 2024

Advantage of calling set() over write()

UVM

UVM , RAL , uvm-ral

2

91

October 27, 2024

RESET Assertion with out clock dependency

SystemVerilog

OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog