Topics tagged RAL

Topic	Replies	Views	Activity
Proper reg_map has not picked up UVM RAL	5	74	July 4, 2024
UVM register model UVM RAL , uvm-ral	0	54	July 1, 2024
RAL Register access UVM RAL	3	152	May 16, 2024
Skipping a register field from comparison with RAL UVM RAL , uvm_ral , RAL-UVM	10	224	May 15, 2024
Macro to read register fields using RAL Coverage UVM , Coverage , assertion , RAL , System-Verilog	1	173	March 26, 2024
How to use get_full_hdl_path for the register UVM RAL	0	172	March 15, 2024
RAL Backdoor access, set hdl paths UVM UVM , RAL	1	187	February 29, 2024
Question related to RAL methods SystemVerilog UVM , RAL , uvm_ral , RAL-UVM	0	180	February 26, 2024
How to access UVM_MEM using the .write method UVM UVM , RAL , uvm_mem	2	260	February 25, 2024
UVM RAL Memory - Sampling after read/write operation UVM SystemVerilog , Coverage , RAL , uvm_mem , Sampling	0	300	February 3, 2024
My question is how to verify “R0” (Read only) registers through backdoor or front door mechanism ? In frontdoor usually we do masking of RO registers to not to write .If RO register is designed with bug with RW type how to verify this issue without write UVM RAL	1	242	January 23, 2024
In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor? UVM UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	0	214	December 29, 2023
Access (to W/R) 2 Specific fields in a 32-bit register UVM RAL , uvm-ral , Systemverilog-UVM-RAL	1	214	December 27, 2023
RAL Integration UVM UVM , RAL , APB , vip-intergrate , register_model	0	307	December 11, 2023
I had an issue regarding RAL, i am unable to create a map which should contains maps of different invidual registers UVM UVM , RAL , RAL-UVM	0	255	December 6, 2023
Predicting Read Only Register in RAL UVM UVM , RAL , prediction-monitor-scoreboard , predictors	1	459	November 30, 2023
How to do Scoreboarding or checking the WR_data and read data matching in RAL UVM UVM , RAL	1	286	November 29, 2023
How to set a register to a value thru a hierarchy receiving as string? UVM UVM , RAL , accessing-the-associative-array-elements , systemverilog-Arrays	3	462	October 4, 2023
Environment and DUT random configuration UVM UVM , RAL , configuration , randomization , UVM-Environment	7	488	September 25, 2023
IN UVM RAL Adapter class, why do we use const ref for uvm_bus_reg_op in reg2bus and only ref for uvm_bus_reg_op in bus2reg? UVM UVM , RAL , adapter	1	246	August 25, 2023
Info regarding built in sequences for memory UVM UVM , RAL	6	578	May 23, 2023
What is the purpose of bus_req.end_event.wait_on(); in uvm_reg_map::do_bus_write UVM UVM , RAL	1	432	March 21, 2023
RAL: set_check_on_read(1) does not work with frontdoor access and passive prediction? UVM UVM , RAL , auto-prediction , set_check_on_read	0	521	March 9, 2023
DUPIDN compilation error for reg models UVM UVM , RAL , RAL-IPXACT , UVM-UVMRAL	0	318	February 27, 2023
UVM RAL sequences with priority UVM UVM , RAL , sequence-arbitration , sequencer-arbitration , UVM-RAL-SEQUENCE	4	717	February 15, 2023
Invalid Register access UVM UVM , RAL , uvm-register-model , -UVM-warnings-disable	4	672	February 6, 2023
How to get uvm_reg_file instance by name in uvm_reg_block UVM UVM , RAL , uvm_ral	0	381	January 9, 2023
Write '1' and '0' is not happening while running bit bash sequence UVM UVM , RAL , UVM-bit_bash	1	496	January 2, 2023
How to implement $sformatf on register models UVM UVM , assertion , RAL	6	652	December 21, 2022
Register Backdoor Issue UVM UVM , RAL , Cookbook-RegistersBackdoorAccess , UVM-RAL-Backdoor-Write-hdl_path	3	3966	November 4, 2022