Topics tagged RAL

Topic	Replies	Views	Activity
Query on Register wr/rd verification by taking security state into consideration UVM RAL	2	28	October 8, 2025
Delay in update of mirrored value in explicit prediction UVM RAL , prediction-monitor-scoreboard , RAL-UVM-PREDICTOR	7	34	October 8, 2025
Backdoor Read consumes simulation time UVM RAL , UVM_BACKDOOR , uvm_ral	2	38	October 8, 2025
Ral explicit prediction UVM UVM , RAL	1	46	September 9, 2025
Uvm_reg_mem_built_in_seq read value and mirrored value is not matching because of reset UVM RAL	2	33	September 4, 2025
How to use get_register_by_name api when register name is an array? UVM RAL	1	31	August 20, 2025
How to have RAL write to DUT without predicting UVM RAL	4	70	August 4, 2025
Reg_block.get_reg_by_name returns unexpected null UVM RAL , uvm-ral , RAL-UVM	0	29	July 30, 2025
RAL set() method followed by update() method modify all 32 bits of a 32 bit register! UVM UVM , RAL	1	46	June 18, 2025
Encoding/Decoding with RAL UVM RAL	4	47	May 14, 2025
Using callbacks to change access to control fields within the same register UVM UVM , RAL , UVM-callback	1	51	May 12, 2025
How to close the print info,just like "[RegModel] Read register via user backdoor...",when i set "+UVM_VERBOSITY=UVM_HIGH"? UVM RAL	4	45	April 22, 2025
Modeling behavior of a register that is dependant on another register UVM RAL	3	60	March 28, 2025
UVM RAL model for register and memory with overlapping address and accessing them using the same interface UVM RAL , RAL-register-UVM , uvm-ral	4	154	March 27, 2025
I cannot find any implementations of a class that extends uvm_reg_file UVM SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure	1	54	March 23, 2025
UVM RAL: Mapping Same Register Block to Two Address Ranges UVM RAL , uvm-ral	0	46	March 12, 2025
Modelling the register fields via callbacks UVM RAL	0	34	March 7, 2025
Coverage for volatile registers in UVM RAL UVM UVM , Coverage , RAL , uvm-ral	3	105	March 6, 2025
UVM RAL writes, reads and prediction UVM UVM , RAL	0	78	February 11, 2025
Implementing Outstanding AXI transactions using RAL UVM UVM , RAL , uvm-ral	1	199	December 19, 2024
RAL Coverage , Multiple Instance issue UVM RAL	2	96	November 26, 2024
Factory in RAL , create vs new UVM RAL	1	92	November 19, 2024
Mirrored value in frontdoor and backdoor UVM RAL	1	125	November 19, 2024
I want to apply RAL for UART Interface that has TX signal only UVM RAL	1	75	November 11, 2024
Register abstraction layer , where can i define the offset of the registers? UVM RAL	1	75	November 4, 2024
Requirement of both local_map & map UVM RAL , uvm-register-model	2	86	October 30, 2024
Advantage of calling set() over write() UVM UVM , RAL , uvm-ral	1	343	October 20, 2024
RESET Assertion with out clock dependency SystemVerilog OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog	1	185	October 18, 2024
Handling multiple RAL request simultaneously UVM UVM , RAL	2	165	September 26, 2024
Can't explain different behavior of 2 RAL registers with W1C fields UVM RAL	1	120	September 20, 2024

Query on Register wr/rd verification by taking security state into consideration

UVM

RAL

2

28

October 8, 2025

Delay in update of mirrored value in explicit prediction

UVM

RAL , prediction-monitor-scoreboard , RAL-UVM-PREDICTOR

7

34

October 8, 2025

Backdoor Read consumes simulation time

UVM

RAL , UVM_BACKDOOR , uvm_ral

2

38

October 8, 2025

Ral explicit prediction

UVM

UVM , RAL

1

46

September 9, 2025

Uvm_reg_mem_built_in_seq read value and mirrored value is not matching because of reset

UVM

RAL

2

33

September 4, 2025

How to use get_register_by_name api when register name is an array?

UVM

RAL

1

31

August 20, 2025

How to have RAL write to DUT without predicting

UVM

RAL

4

70

August 4, 2025

Reg_block.get_reg_by_name returns unexpected null

UVM

RAL , uvm-ral , RAL-UVM

0

29

July 30, 2025

RAL set() method followed by update() method modify all 32 bits of a 32 bit register!

UVM

UVM , RAL

1

46

June 18, 2025

Encoding/Decoding with RAL

UVM

RAL

4

47

May 14, 2025

Using callbacks to change access to control fields within the same register

UVM

UVM , RAL , UVM-callback

1

51

May 12, 2025

How to close the print info,just like "[RegModel] Read register via user backdoor...",when i set "+UVM_VERBOSITY=UVM_HIGH"?

UVM

RAL

4

45

April 22, 2025

Modeling behavior of a register that is dependant on another register

UVM

RAL

3

60

March 28, 2025

UVM RAL model for register and memory with overlapping address and accessing them using the same interface

UVM

RAL , RAL-register-UVM , uvm-ral

4

154

March 27, 2025

I cannot find any implementations of a class that extends uvm_reg_file

UVM

SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure

1

54

March 23, 2025

UVM RAL: Mapping Same Register Block to Two Address Ranges

UVM

RAL , uvm-ral

0

46

March 12, 2025

Modelling the register fields via callbacks

UVM

RAL

0

34

March 7, 2025

Coverage for volatile registers in UVM RAL

UVM

UVM , Coverage , RAL , uvm-ral

3

105

March 6, 2025

UVM RAL writes, reads and prediction

UVM

UVM , RAL

0

78

February 11, 2025

Implementing Outstanding AXI transactions using RAL

UVM

UVM , RAL , uvm-ral

1

199

December 19, 2024

RAL Coverage , Multiple Instance issue

UVM

RAL

2

96

November 26, 2024

Factory in RAL , create vs new

UVM

RAL

1

92

November 19, 2024

Mirrored value in frontdoor and backdoor

UVM

RAL

1

125

November 19, 2024

I want to apply RAL for UART Interface that has TX signal only

UVM

RAL

1

75

November 11, 2024

Register abstraction layer , where can i define the offset of the registers?

UVM

RAL

1

75

November 4, 2024

Requirement of both local_map & map

UVM

RAL , uvm-register-model

2

86

October 30, 2024

Advantage of calling set() over write()

UVM

UVM , RAL , uvm-ral

1

343

October 20, 2024

RESET Assertion with out clock dependency

SystemVerilog

OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog

1

185

October 18, 2024

Handling multiple RAL request simultaneously

UVM

UVM , RAL

2

165

September 26, 2024

Can't explain different behavior of 2 RAL registers with W1C fields

UVM

RAL

1

120

September 20, 2024