Topics tagged RAL

Topic	Replies	Views	Activity
UVM RAL model for register and memory with overlapping address and accessing them using the same interface UVM RAL , RAL-register-UVM , uvm-ral	3	45	March 24, 2025
I cannot find any implementations of a class that extends uvm_reg_file UVM SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure	1	24	March 23, 2025
UVM RAL: Mapping Same Register Block to Two Address Ranges UVM RAL , uvm-ral	0	25	March 12, 2025
Modelling the register fields via callbacks UVM RAL	0	19	March 7, 2025
Coverage for volatile registers in UVM RAL UVM UVM , Coverage , RAL , uvm-ral	3	61	March 6, 2025
UVM RAL writes, reads and prediction UVM UVM , RAL	0	48	February 11, 2025
Implementing Outstanding AXI transactions using RAL UVM UVM , RAL , uvm-ral	1	127	December 19, 2024
RAL Coverage , Multiple Instance issue UVM RAL	2	55	November 26, 2024
Factory in RAL , create vs new UVM RAL	1	61	November 19, 2024
Mirrored value in frontdoor and backdoor UVM RAL	1	64	November 19, 2024
I want to apply RAL for UART Interface that has TX signal only UVM RAL	1	47	November 11, 2024
Register abstraction layer , where can i define the offset of the registers? UVM RAL	1	44	November 4, 2024
Requirement of both local_map & map UVM RAL , uvm-register-model	2	47	October 30, 2024
Advantage of calling set() over write() UVM UVM , RAL , uvm-ral	2	173	October 27, 2024
RESET Assertion with out clock dependency SystemVerilog OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog	1	118	October 18, 2024
Handling multiple RAL request simultaneously UVM UVM , RAL	2	128	September 26, 2024
Can't explain different behavior of 2 RAL registers with W1C fields UVM RAL	1	75	September 20, 2024
How to Selectively skip STS ( RO ) registers in bit_bash UVM UVM , RAL , uvm_reg_bit_bash	0	75	September 19, 2024
How to check the register is implemented in UVM RAL with the address UVM UVM , RAL , uvm_reg	1	130	September 3, 2024
Testing of Read/Write register through RAL when bug is there UVM UVM , RAL	1	126	August 22, 2024
How to get Backdoor Access for Memory? UVM RAL	0	120	August 8, 2024
Proper reg_map has not picked up UVM RAL	5	149	July 4, 2024
UVM register model UVM RAL , uvm-ral	0	129	July 1, 2024
RAL Register access UVM RAL	3	306	May 16, 2024
Skipping a register field from comparison with RAL UVM RAL , uvm_ral , RAL-UVM	10	554	May 15, 2024
Macro to read register fields using RAL Coverage UVM , Coverage , assertion , RAL , System-Verilog	1	310	March 26, 2024
How to use get_full_hdl_path for the register UVM RAL	0	364	March 15, 2024
RAL Backdoor access, set hdl paths UVM UVM , RAL	1	294	February 29, 2024
Question related to RAL methods SystemVerilog UVM , RAL , uvm_ral , RAL-UVM	0	287	February 26, 2024
How to access UVM_MEM using the .write method UVM UVM , RAL , uvm_mem	2	437	February 25, 2024

UVM RAL model for register and memory with overlapping address and accessing them using the same interface

UVM

RAL , RAL-register-UVM , uvm-ral

3

45

March 24, 2025

I cannot find any implementations of a class that extends uvm_reg_file

UVM

SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure

1

24

March 23, 2025

UVM RAL: Mapping Same Register Block to Two Address Ranges

UVM

RAL , uvm-ral

0

25

March 12, 2025

Modelling the register fields via callbacks

UVM

RAL

0

19

March 7, 2025

Coverage for volatile registers in UVM RAL

UVM

UVM , Coverage , RAL , uvm-ral

3

61

March 6, 2025

UVM RAL writes, reads and prediction

UVM

UVM , RAL

0

48

February 11, 2025

Implementing Outstanding AXI transactions using RAL

UVM

UVM , RAL , uvm-ral

1

127

December 19, 2024

RAL Coverage , Multiple Instance issue

UVM

RAL

2

55

November 26, 2024

Factory in RAL , create vs new

UVM

RAL

1

61

November 19, 2024

Mirrored value in frontdoor and backdoor

UVM

RAL

1

64

November 19, 2024

I want to apply RAL for UART Interface that has TX signal only

UVM

RAL

1

47

November 11, 2024

Register abstraction layer , where can i define the offset of the registers?

UVM

RAL

1

44

November 4, 2024

Requirement of both local_map & map

UVM

RAL , uvm-register-model

2

47

October 30, 2024

Advantage of calling set() over write()

UVM

UVM , RAL , uvm-ral

2

173

October 27, 2024

RESET Assertion with out clock dependency

SystemVerilog

OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog