How to have RAL write to DUT without predicting

UVM
1

Greetings.

In my current verification project, one of the requirements from the DUT is that at a certain state during its operation, it must ignore all write sequences it receives on the AXI-4 Lite bus, meaning if the verification environment sends a write sequence to it, the DUT will perform the handshake and receive the data, but will not insert it into its registers.

My verification environment communicates on that AXI-4 Lite bus using a RAL block.
When configuring the registers in the RAL block I set them to have “RW” access.

My issue is that I don’t know how to periodically prevent the RAL block from predicting when writing to the DUT.

At first I was thinking about changing the access to the registers in the RAL to be “RO”, but I realised it is impossible during simulation. I assumed the register.write() function would have a parameter the would disable prediction but that’s not the case also.

The only solution I could find is to use register.do_write(), which I haven’t implemented yet because it seems “unclean” and I didn’t know if it’s a good way to do it.

I’d love some suggestions.
Thank you!

2

Sharing my understanding of the problem

If the write data wouldn’t be reflected in the registers then the BResp returned wouldn’t be OKAY ( d0). I believe in such cases DUT would return SLVERR ( 'b10 )

Within bus2reg function on seeing the SLVERR, rw.status would be assigned UVM_NOT_OK

If you are using auto_prediction ( set_auto_predict() / set_auto_predict(1) )

// During end of  uvm_reg::do_write 
if (system_map.get_auto_predict()) begin
      uvm_status_e status;

      if (rw.status != UVM_NOT_OK) begin
          sample(value, -1, 0, rw.map);
          m_parent.XsampleX(map_info.offset, 0, rw.map);
      end

      status = rw.status; // do_predict will override rw.status, so we save it here
      do_predict(rw, UVM_PREDICT_WRITE);  // My comment :: Updates mirrored values 
      rw.status = status;
 end

This does up end up updating the mirrored values with the write data (based on register access policy of register fields) even though the status of write operation is UVM_NOT_OK

What if you were to use explicit prediction ( with no TLM connection from monitor to predictor component ) during that certain state and revert to auto prediction once it leaves that state ?

3

It appears using “register.field.set_access(“RO”)” is working. I previously used set_access() on the uvm_reg instead of the uvm_reg_field, and for that reason it wasn’t working for me, but it’s all good now.

@Praveen_Kakodra Thank you for your comment, you did open my eyes to the fact that the DUT puts out bresp = 0 when it shouldn’t.

4

Just wanted to ask if changing access during simulation a good idea?

5

I am aware that there are restrictions on calling RAL APIs once root_reg_block.lock_model() is called. Not sure if calling set_access is one of the restricted ones