Implementing Outstanding AXI transactions using RAL

UVM
, ,
1

Hi All,
I am using AXI4 adapter to write/read registers using UVM RAL.
I notice that the write / read RAL API tasks don’t unblock till a respective RRESP/BRESP is received.
( our adapter flags an uvm_error incase RRESP/BRESP is Not OK )
Although AXI4 protocol supports pipelined / outstanding transactions,
user can’t initiate multiple write / read transactions due to following code in UVM library ::

  // Within class uvm_reg_map::do_bus_write / uvm_reg_map::do_bus_read
   if (adapter.provides_responses) begin  // True since driver sends Response
      uvm_sequence_item  bus_rsp;        
      rw.parent.get_base_response(bus_rsp);  // write/read task blocks here
      adapter.bus2reg(bus_rsp,rw_access);
   end
   else begin
      adapter.bus2reg(bus_req,rw_access);
    end

I wanted to know whether one can achieve outstanding transactions via UVM RAL ?
Reference to any papers / docs / edacode that we could use as guidance would be extremely helpful

Thanks,
Arshi

2

The RAL is implemented to treat register accesses as atomic operations. This ensures that there is no potential for register mis-matches if multiple reads/writes were to happen to the same register at the same time.

The use of atomic transactions for register reads/writes is also typically used in real software for the same reason.