UVM RAL model for register and memory with overlapping address and accessing them using the same interface

UVM
, ,
1

Hi, I created a UVM RAL which has some registers with address let’s say from 0 to 3(4 registers) and memory which can have access from address 0, but they are both accessed(register and memory) using the same interface, they are differentiated by type on the interface, Is there a way to implement that in the RAL model?

2

Assuming reg2bus implementation in the register adapter class is correct, I mean it handles the type that differentiates between accessing the memory and accessing the registers e.g.

virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
    // Create interface transaction for example
    if_seq_item if_tr = if_seq_item::type_id::create("if_tr");
    if_tr.TYPE = REG_ACCESS;
    // Continue filling other fields
    ......
    return if_tr;
  endfunction: reg2bus

For prediction especially if you’re using explicit prediction, here you can have different options on how that could be handled,

  • One suggestion is to handle that in bus2reg function in the register adapter class e.g.
 virtual function void bus2reg(uvm_sequence_item bus_item,
                                                     ref uvm_reg_bus_op rw);
   if_seq_item if_tr;
   if (!$cast(if_tr, bus_item)) begin
     `uvm_fatal("NOT_APB_TYPE","Provided bus_item is not of the correct type")
     return;
   end
   if (if_tr.TYPE = REG_ACCESS) begin
      rw.addr = if_tr.addr;
      // Continue filling other fields
       ......
   end else begin
     // set an address value that's outside of the existing register address range
     rw.addr = OUT_OF_RANGE;
   end
 endfunction: bus2reg
  • Another suggestion is to create a new class that extends uvm_reg_adapter and overrides the write function.
3

Thanks for the reply. I will add a type a differentiate it, but one question regarding the addr, if I set the address value to OUT_OF_RANGE for memory, like from the above example, if I set the address to 'h5, the whole purpose of overlapping addresses is gone right?. If I assign it to same address it should be able to differentiate using the type right.

4

So unlike the register model, the memory model does not store state, it simply provides an access layer to the memory, assuming you’re using uvm_mem and in that case, there’s no prediction that will happen to the memory i.e. no usage of bus2reg in that case, so the idea of setting OUT_OF_RANGE value is to prevent the predictor from updating any register that has the same address as a memory location that’s being accessed (caveat that’s in uvm1.2 I am not sure about later versions).
In general, sharing your implementation would help to get a better answer, as many things are unclear, e.g., address mapping; how you handle that in your modelling; do you want to use one adapter for both register model and memory or two? …

5

Right now, I have a single adapter which I will use the transaction type as you mentioned to separate memory and register access.

Address mapping - Generic addition in the model, Right now I see UVM_WARNINGS saying that memory address and register address are overlapping.

My plan is to use the same adapter for both the register and memory, How will the comparison done for memory accesses if I use the same adapter?.