I want to apply RAL for UART Interface that has TX signal only

UVM
1

my transaction has start bit , data (8 bits) , parity bit and stop bit , am sending transcation @ TX.

what if i want to add RAL to my UVM , how can i do the adapter with this transcation ? i don’t have any write/read enable , adds , can i i specify the 8 bits data , to have write/read operation and some bits for adds and some bits for data? i just want to know if this concept is working or not?

here is reg2bus code @adapter

function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
seq_item uart_trans;
uart_trans = seq_item::type_id::create(“uart_trans”);

uart_trans.start_bit = 1'b0;
uart_trans.data[0]   = (rw.kind == UVM_WRITE) ? 1 : 0;
uart_trans.data[2:1] = rw.addr;
uart_trans.data[7:3] = rw.data;
uart_trans.parity_bit = ^uart_trans.data;
uart_trans.stop_bit  = 1'b1;
2

How do you use the UART to do register accesses? If an 8 bit UART word is all you need, then this approach should be fine. If you need more data to be written or read, you may need to make some UART transactor modifications.