RESET Assertion with out clock dependency

SystemVerilog
, , , , , , , , , , ,
1

assertion on reset where reset_a is active low reset signal, it doesn’t depend upon any clk signal ,deassertion if reset_a in asynchronously and assert synchronously.

after reset of reset_a with some delay reset_b signal should get reset.

i try like this
property por_rst;
@(negedge reset_a)
if(reset_a === 1’b0) |-> reset_b <= 1’b0;
endproperty

one thing to be considered is reset_a should also even if the value is ‘z’

like
property por_rst_z;
@( negedge reset_a)
if (reset_a === 1’bz) |-> reset_b <= 1’b0;
endproperty

2

I prefer to use tasks for cases like this.

module mt;
  bit reset_a, reset_b;
  // after reset of reset_a with some delay (< 30ns and > 10ns ) reset_b signal should get reset.
  task automatic t_reset();
    realtime then_time =$realtime;
    fork
      @(negedge reset_b);
      #31;
    join_any
    am_reset:  assert(($realtime - then_time) >10ns && ($realtime -then_time) <= 30ns);
  endtask //automatic

  always @(negedge reset_a) t_reset();

endmodule