assertion on reset where reset_a is active low reset signal, it doesn’t depend upon any clk signal ,deassertion if reset_a in asynchronously and assert synchronously.
after reset of reset_a with some delay reset_b signal should get reset.
i try like this
property por_rst;
@(negedge reset_a)
if(reset_a === 1’b0) |-> reset_b <= 1’b0;
endproperty
one thing to be considered is reset_a should also even if the value is ‘z’
like
property por_rst_z;
@( negedge reset_a)
if (reset_a === 1’bz) |-> reset_b <= 1’b0;
endproperty