Hi,
I am creating full UVM environment (agent, reference model, scoreboard) to a stand alone IP that has SW interface (control & status registers) and HW interface.
The IP needs to be configured by SW, and I’m doing that by UVM RAL MODEL access. My reference model is used to run alongside the DUT and behave similar to it. What is the best practice for my reference model to get updated easily each time there is a SW write or read access? Write access for updating my reference model of a new configurations or some trigger, and read to check if my IP is updating it’s RO (read only) registers correctly (maybe using set_auto_predict?).
Thanks