Proper reg_map has not picked up

UVM
1

i am trying to do frontdoor write ,but the register interface which is mapped to this register is not picked up, it is picking some other protocol interface but it is not picking required mapped hardware interface.
can anyone please suggest what files need to be changed ?

2

Please elaborate in some more detail what you mean with register interface and other protocol interface. If your RAL model is implemented correctly you do not directly access any pinlevel interface.

3

yes , the issue is the there are two maps in register, for example axi_map ,apb_map . so the issue is it is always picking axi_map .even if i explicitly mention the access path as apb_map. i want it to be happen through apb_map
what is the solution here ?

4

Could you please show some code describing the situation.

5

sure let me paste the dummy code

6 
class reg_a extends uvm_reg;
// all the field are added
//new ,build function are coded
endclass
//top reg block
class ip_top_reg extends uvm_reg_block;
  rand reg_a reg_a_ins;
  // two maps which are there for two protocol interface ,so this register can be accessed in two access_path...
  uvm_reg_map axi_cfg_inst;
  uvm_reg_map apb_mem_inst;
   
  reg_a_ins = new("reg_a_ins");
  reg_a_ins.build();
  reg_a_ins.configure(this, null);
  axi_cfg_inst = create_map("axi_cfg_inst", 'h0, 1, UVM_LITTLE_ENDIAN);
  axi_mem_inst = create_map("axi_mem_inst", 'h0, 1, UVM_LITTLE_ENDIAN);
  axi_cfg_inst.add_reg(reg_a_ins, 'h4 , "RW");
  apb_mem_inst.add_reg(reg_a_ins, 'h5 , "RW");

endclass

/// sequence use
class ral_accesss extends base_seq;   //this base sequence is derived from uvm_sequence 
uvm_reg_block reg_block;
  if(!($cast(reg_block, uvm_reg_block::find_block($sformatf("ip_top_reg"), reg_block))) || reg_block==null)
  `uvm_error(get_name(), $sformatf("Could not find block [ip_top_reg] within root block=[%s]", reg_block.get_full_name()));
 
    register = reg_block.get_reg_by_name("reg_a_ins");
    register.get_maps(maps);
     foreach(maps[i])
       `uvm_info(get_type_name(), $sformatf("register name :%s, map name:%s ", register.get_name,maps[i].get_name), UVM_NONE);
endclass

here it was picking for map “axi_cfg_inst” but my intention was to write through other map? any fix for it