Topics tagged Coverage

Topic	Replies	Views	Activity
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	1	92	July 5, 2024
How to debug the coverage miss of bins in a Covergroup? Coverage Coverage	1	67	June 24, 2024
How to show coverage results in reparate Instances Coverage UVM , Coverage	1	117	June 12, 2024
Declaration of coverpoint for multidimensional array UVM Coverage	5	97	June 6, 2024
Functional coverage Coverage Coverage , functional-coverage	1	319	August 4, 2023
Is it better to write functional coverage in a UVM class or a module? Coverage Coverage	1	102	June 5, 2024
How to write functional coverage for FSM (for both State coverage and Transition coverage) Coverage Coverage , SystemVerilog-FunctionalCoverage	7	5432	June 4, 2024
How to exclude such conditions with Coverpoints? UVM SystemVerilog , Coverage , ignore_bins , cross-coverage-bins	0	88	June 3, 2024
Coverage collector or subscriber usage UVM UVM , Coverage	0	153	May 4, 2024
Introducing the Coverage Cookbook Coverage Coverage	1	4217	March 19, 2013
How to cover unsigned int UVM SystemVerilog , UVM , Coverage	1	148	April 30, 2024
How to know about which seed is running and getting randomize when my seed is processed randomly? Coverage Coverage , SEED , code-coverage , run_test4-clean-lib-cmp-vsim-VSIMBATCH4-coverage-vopt-sva-sv_seed-random	5	517	April 26, 2024
Empty bin warning for disabled cover point Coverage SystemVerilog , Coverage	1	130	April 19, 2024
FSM state transition coverage issue Coverage Coverage , coverpoint , functional-coverage , UVM_OBJECT-and-UVM_COMPONENT , uvm_monitor	3	6867	April 1, 2024
Macro to read register fields using RAL Coverage UVM , Coverage , assertion , RAL , System-Verilog	1	172	March 26, 2024
Getting Transition Bins for a N bit Counter SystemVerilog SystemVerilog , Coverage	1	147	March 12, 2024
Expression coverage Coverage Coverage	4	311	February 21, 2024
Coverpoint bins with clause SystemVerilog SystemVerilog , Coverage , SystemVerilog-FunctionalCoverage	3	282	February 13, 2024
Cover point error SystemVerilog Coverage , Coverage-bins	2	171	February 6, 2024
UVM RAL Memory - Sampling after read/write operation UVM SystemVerilog , Coverage , RAL , uvm_mem , Sampling	0	299	February 3, 2024
Connecting inout real to real data type SystemVerilog UVM , Coverage , assertion , System-Verilog , SVA	1	213	January 30, 2024
Error Coverage Coverage	6	3957	January 5, 2024
Coverpoint for dist Coverage SystemVerilog , Coverage , System-Verilog	1	358	January 2, 2024
Coverage cross ignore values inside an external array SystemVerilog SystemVerilog , Coverage , cross , ignore_bins	4	439	December 12, 2023
About non-masking condition in exclude list Coverage Coverage	3	458	December 10, 2023
Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector Coverage Coverage , System-Verilog , Coverage-bins , coverage-bins-uvm-array	1	514	November 29, 2023
'Illegal Bin' in cross coverage for unaligned address Coverage Coverage	1	488	November 29, 2023
Functional coverage : bins creation Coverage Coverage , autobins , SystemVerilog-FunctionalCoverage	2	510	November 29, 2023
Coverage sample if request came on same address with-in 10ns Coverage Coverage , Coverage-bins	1	303	November 23, 2023
How to cover these id bins Coverage Coverage , Distribute-constraint-with-coverage	1	305	November 15, 2023