Topics tagged Coverage

Topic	Replies	Views	Activity
How to know about which seed is running and getting randomize when my seed is processed randomly? Coverage Coverage , SEED , code-coverage , run_test4-clean-lib-cmp-vsim-VSIMBATCH4-coverage-vopt-sva-sv_seed-random	5	352	April 26, 2024
Empty bin warning for disabled cover point Coverage SystemVerilog , Coverage	1	27	April 19, 2024
FSM state transition coverage issue Coverage Coverage , coverpoint , functional-coverage , UVM_OBJECT-and-UVM_COMPONENT , uvm_monitor	3	6670	April 1, 2024
Macro to read register fields using RAL Coverage UVM , Coverage , assertion , RAL , System-Verilog	1	66	March 26, 2024
Getting Transition Bins for a N bit Counter SystemVerilog SystemVerilog , Coverage	1	86	March 12, 2024
Expression coverage Coverage Coverage	4	184	February 21, 2024
Coverpoint bins with clause SystemVerilog SystemVerilog , Coverage , SystemVerilog-FunctionalCoverage	3	180	February 13, 2024
Cover point error SystemVerilog Coverage , Coverage-bins	2	106	February 6, 2024
UVM RAL Memory - Sampling after read/write operation UVM SystemVerilog , Coverage , RAL , uvm_mem , Sampling	0	179	February 3, 2024
Connecting inout real to real data type SystemVerilog UVM , Coverage , assertion , System-Verilog , SVA	1	112	January 30, 2024
Error Coverage Coverage	6	3862	January 5, 2024
Coverpoint for dist Coverage SystemVerilog , Coverage , System-Verilog	1	236	January 2, 2024
Coverage cross ignore values inside an external array SystemVerilog SystemVerilog , Coverage , cross , ignore_bins	4	328	December 12, 2023
About non-masking condition in exclude list Coverage Coverage	3	321	December 10, 2023
Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector Coverage Coverage , System-Verilog , Coverage-bins , coverage-bins-uvm-array	1	367	November 29, 2023
'Illegal Bin' in cross coverage for unaligned address Coverage Coverage	1	372	November 29, 2023
Functional coverage : bins creation Coverage Coverage , autobins , SystemVerilog-FunctionalCoverage	2	367	November 29, 2023
Coverage sample if request came on same address with-in 10ns Coverage Coverage , Coverage-bins	1	228	November 23, 2023
How to cover these id bins Coverage Coverage , Distribute-constraint-with-coverage	1	233	November 15, 2023
System Verilog , Coverage Coverage Coverage , svcoverage	1	413	November 9, 2023
Cover modes in spi Coverage Coverage , Dave-Rich , chris-sue , Chris-Spear	1	291	October 27, 2023
System Verilog coverage Coverage Coverage , System-Verilog , systemverilog-coverage-cross , Coverage-bins	5	461	September 25, 2023
Null object error Coverage Coverage , System-Verilog , Null-Object-Access , coverage-UVM-module-class	1	311	September 16, 2023
SVA Covered and Uncovered properties in coverage report SystemVerilog SystemVerilog , Coverage , SVA , UVM-Verdi	2	230	September 14, 2023
Functional Coverage for multiple monitors Coverage Coverage	1	202	August 29, 2023
At which time subscriber should sample the packet for coverage? UVM UVM , Coverage , Subscriber-in-uvm	4	198	August 28, 2023
How to exclude bins which are getting created automatically? Coverage Coverage , SystemVerilog-FunctionalCoverage	2	279	August 25, 2023
Command for exclude any line from code in code coverage Coverage Coverage	1	189	August 24, 2023
Option.comment and type_option.comment Coverage Coverage , Coverage-bins	1	281	August 16, 2023
Coverage analyze Coverage Coverage , Coverage-bins , coverage-analyze	1	205	August 7, 2023