Topics tagged Coverage

Topic	Replies	Views	Activity
Code coverage : Block Coverage Coverage	0	26	November 25, 2025
Is there any way to merge two types of code coverage and show the total between them Coverage Coverage	2	24	November 21, 2025
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules? UVM OVM , SystemVerilog , UVM , Coverage	0	36	November 17, 2025
VHDL Code Coverage - Generate Statements Coverage Coverage	2	28	November 6, 2025
Chained Implications in SVA SystemVerilog SystemVerilog , Coverage , assertion , SVA , axi , AHB	0	45	November 3, 2025
In my design, I have an assign statement like assign var = (a == b) ? 1 : 0;. During simulation, var takes both values 1 and 0 as expected, but in Questa code coverage, this statement is still shown as not covered. Why is this happening? Coverage Coverage , questasim	2	31	October 29, 2025
Excluding the already defined bins Coverage SystemVerilog , Coverage , Dave-Rich	5	54	October 12, 2025
Coverpoint for groups of address SystemVerilog Coverage	1	46	October 10, 2025
Trying to cover the following Transition coverage SystemVerilog Coverage , Transition-Coverage	0	38	October 6, 2025
Multiple Instances of a Covergroup Coverage Coverage	5	4932	September 11, 2025
HDLBits like website to practice SystemVerilog (assertions/constraints/ some riddles)? SystemVerilog Coverage , assertion , constraint-randomization	2	168	September 2, 2025
How the sample function for collecting coverage is implemented Coverage SystemVerilog , Coverage	3	69	August 25, 2025
Does cross coverage create auto bins even if i declare few user defined bins? Coverage Coverage	2	1706	August 19, 2025
Trasition between signals Coverage Coverage	2	1135	August 19, 2025
Coverage bins sampling an uninitialized virtual interface object SystemVerilog UVM , Coverage	7	113	July 15, 2025
SV cross coverage with 'intersect' keyword SystemVerilog Coverage , cross-coverage-bins	6	95	June 26, 2025
Sample level triggered signal Coverage Coverage	6	114	June 25, 2025
Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector Coverage Coverage , System-Verilog , Coverage-bins , coverage-bins-uvm-array	2	918	May 17, 2025
Functional Coverage for larger bit size SystemVerilog UVM , Coverage	1	78	May 17, 2025
Combining illegal_bins with default SystemVerilog Coverage , illegal-bins , Default-bin	1	85	May 12, 2025
How to specify coverbin for all negative integers Coverage Coverage	1	117	May 10, 2025
Create a coverpoint with its bit width varies SystemVerilog Coverage , coverpoint , covergroup	2	112	April 11, 2025
What is False Coverage and hole in coverage ? How to solve them? Coverage SystemVerilog , Coverage	1	218	April 2, 2025
Create a coverpoint to sample non default value SystemVerilog Coverage , coverpoint	2	67	April 2, 2025
Cross coverage of coverpoints sampling on different addresses SystemVerilog SystemVerilog , Coverage , cross-coverage	2	130	March 26, 2025
Coverage for volatile registers in UVM RAL UVM UVM , Coverage , RAL , uvm-ral	3	130	March 6, 2025
Functional Coverage as Toggle Coverage Coverage SystemVerilog , Coverage , System-Verilog	3	227	February 17, 2025
Coverpoint bins for fractional values SystemVerilog UVM , Coverage	4	170	December 14, 2024
Only coverpoint or cross identifier or coverpoint or cross bins as xmr allowed Coverage Coverage , muku_kr	1	96	December 5, 2024
Cover property/sequence for transaction objects SystemVerilog SystemVerilog , Coverage , property	0	112	November 26, 2024