Topics tagged Coverage

Topic	Replies	Views	Activity
I cant see EPwave in eda playground UVM SystemVerilog , Coverage , waveform	2	19	May 23, 2025
Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector Coverage Coverage , System-Verilog , Coverage-bins , coverage-bins-uvm-array	2	773	May 17, 2025
Functional Coverage for larger bit size SystemVerilog UVM , Coverage	1	26	May 17, 2025
Combining illegal_bins with default SystemVerilog Coverage , illegal-bins , Default-bin	1	32	May 12, 2025
How to specify coverbin for all negative integers Coverage Coverage	1	28	May 10, 2025
Create a coverpoint with its bit width varies SystemVerilog Coverage , coverpoint , covergroup	2	71	April 11, 2025
What is False Coverage and hole in coverage ? How to solve them? Coverage SystemVerilog , Coverage	1	85	April 2, 2025
Create a coverpoint to sample non default value SystemVerilog Coverage , coverpoint	2	51	April 2, 2025
Cross coverage of coverpoints sampling on different addresses SystemVerilog SystemVerilog , Coverage , cross-coverage	2	85	March 26, 2025
Coverage for volatile registers in UVM RAL UVM UVM , Coverage , RAL , uvm-ral	3	79	March 6, 2025
Functional Coverage as Toggle Coverage Coverage SystemVerilog , Coverage , System-Verilog	3	125	February 17, 2025
Coverpoint bins for fractional values SystemVerilog UVM , Coverage	4	117	December 14, 2024
Only coverpoint or cross identifier or coverpoint or cross bins as xmr allowed Coverage Coverage , muku_kr	1	57	December 5, 2024
Cover property/sequence for transaction objects SystemVerilog SystemVerilog , Coverage , property	0	70	November 26, 2024
Cross coverage of assertion property Coverage Coverage , assertion	1	165	November 7, 2024
SV Functional Coverage Coverage SystemVerilog , Coverage	6	311	November 6, 2024
How to explicitly mention bins in cross coverage SystemVerilog Coverage	1	94	October 16, 2024
Automatic bin getting created more than 2 for 1 bit variable Coverage SystemVerilog , Coverage	1	140	September 3, 2024
$load_coverage_db(filename) usage Coverage SystemVerilog , Coverage	1	130	August 30, 2024
Creating Different Instance of the cover-properties SystemVerilog SystemVerilog , Coverage , assertion	1	94	August 29, 2024
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	1	411	July 5, 2024
How to debug the coverage miss of bins in a Covergroup? Coverage Coverage	1	303	June 24, 2024
How to show coverage results in reparate Instances Coverage UVM , Coverage	1	255	June 12, 2024
Declaration of coverpoint for multidimensional array UVM Coverage	5	275	June 6, 2024
Functional coverage Coverage Coverage , functional-coverage	1	463	August 4, 2023
Is it better to write functional coverage in a UVM class or a module? Coverage Coverage	1	340	June 5, 2024
How to write functional coverage for FSM (for both State coverage and Transition coverage) Coverage Coverage , SystemVerilog-FunctionalCoverage	7	5741	June 4, 2024
How to exclude such conditions with Coverpoints? UVM SystemVerilog , Coverage , ignore_bins , cross-coverage-bins	0	235	June 3, 2024
Coverage collector or subscriber usage UVM UVM , Coverage	0	240	May 4, 2024
Introducing the Coverage Cookbook Coverage Coverage	1	4375	March 19, 2013