How to explicitly mention bins in cross coverage

SystemVerilog
1

I am working on a project where I am to verify and obtain coverage metrics for a router. And the condition is set such that the src and destination shouldn’t be the same node. I have 2 coverpoints, src_addr and dst_addr. And cross coverage CROSS_COV: cross src_addr, dst_addr. I want individual bins for each source destination pair in the cross, and the pairs where src==dst to be part of illegal bins. How can I achieve this?

CROSS_COV: cross SRC_ADDR, DST_ADDR {
		bins valid[] = CROSS_COV with (SRC_ADDR != DST_ADDR);
		illegal_bins ib = CROSS_COV iff (SRC_ADDR == DST_ADDR);
};

I came up with this, but it wont work, does anyone know how to work around this problem?

2

A cross implicitly creates individual bins for all the pairs. You write explicit bins to merge, ignore, or catch illegal pairs.

  CROSS_COV: cross SRC_ADDR, DST_ADDR {
		illegal_bins ib = CROSS_COV with (SRC_ADDR == DST_ADDR);
}

You want to use with, not iff to select bins to be constructed. iff just guards sampling of the bins.