Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector

Coverage
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Hi All,

Can anyone please tell me how to Add a ignore_bin for this vector signal WData_Stb (64 bit). the only legal values are when all the 1’s are continuous. It is allowed to have 0’s at either end of the vector, but there cannot be any 0’s between 1’s in the vector.

Instead of writing all the valid possible cases I thought it is better to add a ignore_bin for the invalid cases. How to do achieve this in system verilog in a simple way ?

WData_Stb_cp: coverpoint (intf.mon_cb.WData_Stb) iff (intf.mon_cb.WData_Rdy && intf.mon_cb.WData_Vld)

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In reply to sriram_6869:

To enforce the constraint that all 1’s in the WData_Stb vector must be continuous, you can use the ignore_bins feature in SystemVerilog. The ignore_bins statement allows you to specify bins that should be ignored during coverage analysis.

Here’s an example of how you can add an ignore_bin to your covergroup to handle the cases where there are 0’s between 1’s in the WData_Stb vector:

covergroup WData_CG with function sample (logic [63:0] WData_Stb);
    option.per_instance = 1;

    WData_Stb_cp : coverpoint WData_Stb {
        bins valid_data = {[1:$]} iff (isValid(WData_Stb));

        // Ignore bins for invalid cases
        ignore_bins invalid_data = {[1'b0]};
    }

    // Additional coverpoints or crosses as needed

    // Function to check if the vector has continuous 1's
    function bit isValid(logic [63:0] data);
        logic [63:0] mask;
        mask = data;
        mask &= mask << 1;
        return (mask == 0);
    endfunction
endgroup

// Instantiate the covergroup
WData_CG wdata_cg_inst;

// Sample the data
initial begin
    // Assuming some kind of sampling loop
    repeat (1000) begin
        logic [63:0] WData_Stb = /* your logic to generate WData_Stb */;
        
        // Sample values
        wdata_cg_inst.sample(WData_Stb);
        
        // Add other sampling code as needed
    end

    // Report coverage at the end
    wdata_cg_inst.report();
end

In this example:

The WData_Stb_cp coverpoint has a bin named valid_data that includes the range [1:$] (all 1’s). This bin is conditioned on the isValid function, which checks if the vector has continuous 1’s.

The ignore_bins statement is used to specify the invalid_data bin, which includes the value [1’b0]. This bin is ignored during coverage analysis.

The isValid function checks if the vector has continuous 1’s by creating a mask and comparing it with its left-shifted version. If they are equal, then there are no 0’s between 1’s. If they are not equal, then there are 0’s between 1’s, and the bin is ignored.

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Freelancer/verification engineer
https://www.linkedin.com/in/rahulvala/