How to write functional coverage for FSM (for both State coverage and Transition coverage)

Coverage
,
1

Hi all,
How to write functional coverage for FSM , im stuck at like how to extract the states into functional coverage.


module example (
 output wire [1:0] out,
 input wire clk,
 input wire in,
input wire rst_n
 );

/ / s t a t e b i t s
 parameter
 S0 = 2’b00, / / out [ 1 : 0 ]=0 0
 S1 = 2’b01, / / out [ 1 : 0 ]=0 1
 S2 = 2’b10; / / out [ 1 : 0 ]=1 0

 reg [1:0] state;
 reg [1:0] nextstate;

 / / comb alway s b l o c k
 always @* begin
 nextstate = state;
 c as e (state)
 S0: begin
 i f (in = 1) begin
 nextstate = S1;
 end
 e l s e begin
 nextstate = S0;
 end
 end
 S1: begin
 i f (in = 1) begin
 nextstate = S2;
 end
 e l s e begin
 nextstate = S0;
 end
 end
 S2: begin
 begin
 nextstate = S0;
 end
 end
 endcase
 end

 / / As s ign reg ’ d o u t p u t s t o s t a t e b i t s
 a s s i g n out[1:0] = state[1:0];

 / / s e q u e n t i a l alway s b l o c k
 always @(posedge clk or negedge rst_n) begin
 i f (!rst_n)
 state <= S0;
 e l s e
 state <= nextstate;
 end

 endmodule
2

You don’t need to write functional coverage for this. Tools can generate this kind of coverage for you automatically. It’s called FSM coverage and it consists of coverage that each state has been reached and that all possible state arcs have been traversed.

3

In reply to Tudor Timi:

I know that, but explicitly if i want to write functional coverage for FSM, then how to proceed?

4

In reply to rohit_kumar:

if you don’t want to rely on the tool FSM coverage and want to define your own FSM coverage. collector , Inside the interface of testbench where you have access low level information.
Define the transition coverage (Arc of the FSM) in cover group inside the interface.

5

In reply to kddholak:

Hi,
In interface only signals will be defined rite, no state representations. how to cover states transitions?

interface example_intf(input bit clk);
logic[1:0] out,
logic in,
logic rst_n
endinterface

6

Sir, Kindly explain if you got it.

7

I guess you are looking for FSM coverage in your DUT, right. In this case you have to make the internal signals visible on the border or in your testbench. You can reach this by binding a coverage component to your DUT. Using the tool coverage is not so good because this has no flexibility when canging your tool.

8

if the requirement is not to probe into the internal signals. then based on input , and output user need to come up with FSM , and implement in interface logic. it can be done using assertions.