Cross coverage of coverpoints sampling on different addresses

SystemVerilog
, ,
1

Hi, I m sharing a sample problem I am facing while doing a cross of coverpoints which are sampled at different addresses individually:
These are few coverpoints:

IMC_TILE2A_RES : coverpoint cov_data[10 +: 2] iff ((cov_addr == (address + offset + 96)) && (cov_we == 1) && (cov_trans == 2'b10)) {
  bins RES_0_3[4] = {[0 : 3]};
}
IMC_TILE2A_FIRST : coverpoint cov_data[6] iff ((cov_addr == (address + offset + 96)) && (cov_we == 1) && (cov_trans == 2'b10)) {
  bins FIRST_0_1[2] = {[0 : 1]};
}
IMC_CTRLEXT0_BIAS : coverpoint cov_data[0 +: 16] iff ((cov_addr == (address + offset + 48)) && (cov_we == 1) && (cov_trans == 2'b10)) {
  bins BIAS_0 = {0};
  bins BIAS_1_4 = {[1 : 4]};
  bins BIAS_5_8 = {[5 : 8]};
  bins BIAS_9_12 = {[9 : 12]};
  bins BIAS_13_16 = {[13 : 16]};
  bins BIAS_17_20 = {[17 : 20]};
}

Here, If you see the coverpoints IMC_TILE2A_RES and IMC_TILE2A_FIRST have same sampling address (cov_address) but IMC_CTRLEXT0_BIAS is at different cov_address.
So when I do cross of coverpoints at same sampling addresses , it works ,
RESXFIRST : cross IMC_TILE2A_RES, IMC_TILE2A_FIRST;
but it does not work:
RESXBIAS: cross IMC_TILE2A_RES, IMC_CTRLEXT0_BIAS;
P.S. all of these coverpoints are individually triggered.
//to sample this cross I added condition to cross:
RESXFIRST : cross IMC_TILE2A_RES, IMC_TILE2A_FIRST iff(((cov_addr == (address + offset + 48)) && (cov_we == 1) && (cov_trans == 2'b10)) && ((cov_addr == (address + offset + 96)) && (cov_we == 1) && (cov_trans == 2'b10))); // this did not work
I also made a logic to be added inside iff of cross:
logic sample_signal ;

always @clk begin
if begin ((((cov_addr == (address + offset + 48)) && (cov_we == 1) && (cov_trans == 2'b10)) && ((cov_addr == (address + offset + 96)) && (cov_we == 1) && (cov_trans == 2'b10)))
sample_signal <= 1;
end
else begin
sample_signal <= 0;
end
end
RESXFIRST : cross  IMC_TILE2A_RES,  IMC_TILE2A_FIRST iff (sample_signal);// did not work as sampling signal never gets high because both sampling addresses never gets high together.

Then I tried a trick which worked:
I redefined these coverpoints and now sampling conditions is replaced by the respective RTL signal name which is formed after register read in design:

IMC_TILE2A_RES_TB: coverpoint top0.tile2ares {
  bins RES_0_3[4] = {[0 : 3]};
}
IMC_TILE2A_FIRST_TB: coverpoint top0.tile2afirst {
  bins FIRST_0_1[2] = {[0 : 1]};
}
IMC_CTRLEXT0_BIAS_TB : coverpoint top0.ctrlbias0 {
  bins BIAS_0 = {0};
  bins BIAS_1_4 = {[1 : 4]};
  bins BIAS_5_8 = {[5 : 8]};
  bins BIAS_9_12 = {[9 : 12]};
  bins BIAS_13_16 = {[13 : 16]};
  bins BIAS_17_20 = {[17 : 20]};
}

and now when I do cross it is working:
RESXBIAS_TB: cross IMC_TILE2A_RES_TB, IMC_CTRLEXT0_BIAS_TB;

I know this is alot to explain :( but my fear is that this workaround is not good as I am probing design signals. suggest me the solution and correct me if I am wrong

Regards
Sanchika

2

A covergroup has only one sampling event. All of the coverpoints and crosses get evaluated at once. A cross is the product of two or more coverpoints getting sampled at the same event. If you try cross two coverpoints that never get sampled at the same event (because of the iff expression), no bins in the cross ever get hit.

You have not explained the conditions that trigger the sampling event for any of your code snippets. Instead of focusing on the specific SystemVerilog syntax, you need to step back and clearly explain the underlying requirements and behaviors you are trying to capture with your coverage collection. What are the key scenarios, events, or conditions that you need to monitor and measure coverage for? Providing more context about the overall coverage objectives will help us help you ensure your approach aligns with the actual requirements.

3

Hi Dave,
Thanks for your reply.

These coverpoints are part of a single covergroup and the sampling condition for coverpoints are inside “iff” which involves respective cov_addr

covergroup IMC_registers_cov(int address, int offset) @(negedge cov_clk);

IMC_TILE2A_RES : coverpoint cov_data[10 +: 2] iff ((cov_addr == (address + offset + 96)) && (cov_we == 1) && (cov_trans == 2'b10)) {}
IMC_TILE2A_FIRST : coverpoint cov_data[6] iff ((cov_addr == (address + offset + 96)) && (cov_we == 1) && (cov_trans == 2'b10)) {}
IMC_CTRLEXT0_BIAS : coverpoint cov_data[0 +: 16] iff ((cov_addr == (address + offset + 48)) && (cov_we == 1) && (cov_trans == 2'b10)) {}

//I am writing cross bins here

endgroup

generate
  for (IMC_i = 0; IMC_i < 1; IMC_i = IMC_i + 1) begin: IMC_cov
    if (T1_IMC_GET_CONFIG(IMC_i) == "") begin
      IMC_registers_cov IMC_cov;

      initial begin
        IMC_cov = new(T1_SLAVE_BASE_ADDRESS, T1_GET_BASE(IMC_i));
        IMC_cov.set_inst_name($sformatf("IMC_cov_%0d", IMC_i));
      end
    end
  end
endgenerate

Verification requirement is the cross of IMC_TILE2A_RES and IMC_CTRLEXT0_BIAS to check BIAS is covered against all values of resolution (which is IMC_TILE2A_RES)