Both registers, REG1 and REG2, are interrupt status registers with all W1C fields.
- Example REG1 field and REG1’s configuration in
uvm_reg_block1
SUSPEND_EVENT.configure(this, 1, 1, "W1C", 0, 1'b0, 1, 0, 0);
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block1_reg_map = create_map("block1_reg_map", 'h0, 4, UVM_LITTLE_ENDIAN);
default_map = block1_reg_map;
block1_reg_map.add_reg(REG1, 'h38, "RW");
- Example REG2 field and REG2’s configuration in
uvm_reg_block2
PLL_LOCK.configure(this, 1, 0, "W1C", 0, 1'b0, 1, 0, 0);
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block2_reg_map = create_map("block2_reg_map", 'h0, 4, UVM_LITTLE_ENDIAN);
default_map = block2_reg_map;
block2_reg_map.add_reg(REG2, 'h44, "RW");
RAL model should behave similarly upon reading either of them. But, in my case, REG1 read throws up error anytime the read-data is non-zero, but REG2 read does not! REG2 read does not report any error even with non-zero read-data!
# UVM_ERROR verilog_src/uvm-1.1d/src/reg/uvm_reg.svh(2889) @ 1487485648 [RegModel] Register "register_map.uvm_reg_block1_inst.REG1" value read from DUT (0x0000000000000001) does not match mirrored value (0x0000000000000000)
# UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg.svh(2902) @ 1487485648 [RegModel] Field SUSPEND_EVENT (register_map.uvm_reg_block1_inst.REG1[0:0]) mismatch read=1'h1 mirrored=1'h0
I’ve done some debug at my end, by printing the read-data, check policy (which is UVM_CHECK for both of them), but nothing could lead me to the cause.
Both the registers are part of different uvm_reg_block s , but I’ve checked both the reg_blocks and they are pretty similar.
This is how I’m reading both the registers.
rmap.uvm_reg_block1_inst.REG1.read(status,VALUE);
...
rmap.uvm_reg_block2_inst.REG2.read(status,VALUE);
where
class top_level_block extends uvm_reg_block;
`uvm_object_utils(top_level_block)
uvm_reg_block1 uvm_reg_block1_inst;
uvm_reg_block2 uvm_reg_block2_inst;
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top_level_block_map = create_map("top_level_block_map", 'h0, 4, UVM_LITTLE_ENDIAN);
default_map = top_level_block_map;
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top_level_block_map.add_submap(uvm_reg_block1_inst.block1_reg_map, 'h0);
top_level_block_map.add_submap(uvm_reg_block2_inst.block2_reg_map, 'h400);
What could I be doing different while creating/accessing both registers? Where should I look next?
I’m using UVM-1.1d bundled with Questasim.