Testing of Read/Write register through RAL when bug is there

UVM
,
1

Good Day!!
In our design we have a 10 different cores and each core has 10 read/write register. If the user wants to writes to core-1 register-2.

  1. User needs to write to general purpose register A providing information about core number and register number. In this case Core-1 register-2.
  2. User needs to write to general purpose register B providing information about what data needs to be written into core-1 register-2.

But In actual RTL design, user could only be able to write this register. Reading this register will always give 0. Because we have bug on that and the design team has decided not to fix this issue.

I want to verify the value that I am writing to this register is actually getting written or not. How can i verify this? We already have a RAL model for this. Using RAL how I am suppose to verify that correct value is written to the register.

2

If back-door access is available to read the register, you can verify it that way. If the designers are not going to fix the RTL to meet the specification, they need to fix the specification. The register access needs to become either write-only “WO”, or write-and-clear “WC”. If back door access.

And in any case, you still need to verify the design behaves as it is supposed to based on the register settings.