Thx for your trial on your side. In fact you are true, i “lighted” the case in “uvm_tb_build_bl_tb.tgz” to remove unused seqs. That’s the reason for the mismatch between my reported line and the one corresponding in your src files.
So i ran again from scratch the usecase from proper “uvm_tb_build_bl_tb.tgz”. And i still get the issue but line 363 that time.
I think i know where it comes from: i use VIVADO Simulator 2021.1 with uvm 1.2 and you probably use Questasim.