Has anyone implemented a Write 1 only self-clearing policy for a uvm_reg_field?

UVM
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1

Hi,

I am trying to implement a policy for W10, but in our case the bit is supposed to self-clear. I am using W1S currently but since that remains set , it does not update for a consequent write? any ideas?

2

Have you tried ”W1C”?

”W1C” W: 1/0 clears/no effect on matching bit, R: no effect

If that doesn’t give you what you’re looking for then a user-defined access policy is needed. There are many ways to implement that I will quote one from this great paper Advanced UVM Register Modeling
which is based on using post_write hook. If you’re curious to know other ways, I recommend reading the paper. It provides very good possible solutions to common problems in UVM register modelling

class wres_reg_field extends uvm_reg_field;

  `uvm_object_utils(wres_reg_field)

  local static bit m_wres = define_access("WRES");
  function new(string name = "wres_reg_field"); ...
  
  virtual task post_write(uvm_reg_item rw);
    // set the mirror to reset value after a write
    if (!predict(rw.get_reset())) `uvm_error(...) 
  endtask

endclass

class wres_reg extends uvm_reg;
  `uvm_object_utils(wres_reg)
  rand wres_reg_field wres_field; // special field

  function new(string name="wres_reg"); ...
  
  virtual function void build();
    wres_field = wres_reg_field::type_id::create("wres_field");
    wres_field.configure(
    this,8,0,"WRES",0,8'hAB,1,1,1);
  endfunction
endclass


class my_reg_block extends uvm_reg_block;
  virtual function void build();
  ...
  wres_reg = wres_reg::type_id::create("wres_reg");
  wres_reg.configure(this, null, "wres_reg");
  wres_reg.build();
  default_map.add_reg(wres_reg, 'h24, "RW");
  ...

endclass

Hope that helps :)

1 Like
3

Cool thanks will take a look. I tried W1C but was not seeing it set to 1 because of it being cleared I guess. not what I wanted.