Topics tagged class

Topic	Replies	Views	Activity
System Verilog coverge sampling using class instead of Mod SystemVerilog SystemVerilog , class , covergroup , Cookbook-CoverageFunctional-Coverage-Metrics , coverbins-range , system-verilog-coverage-with-clause-coverpoints	2	406	November 9, 2023
Does type_id::create() end up eventually call the class's new function? UVM UVM , class , type_idcreate , uvm-new-constrtor , Understanding-syntax-type_id-create	7	695	October 26, 2023
How to override severity report from UVM_ERROR to UVM_WARNING of a module UVM UVM , assertion , class , module , severity_overrride	2	1008	October 20, 2023
How to use packages in class SystemVerilog SystemVerilog , class , Package	3	753	August 22, 2023
Understanding Automatic or Automatic Lifetime of Class objects - SV SystemVerilog SystemVerilog , assertion , class , OOPS , system-verilog-interface-generate	4	453	July 25, 2023
SV Introspection SystemVerilog SystemVerilog , class , datatype	1	456	April 24, 2023
Local vs protected in SV class SystemVerilog SystemVerilog , class	5	14157	March 20, 2023
How to change the bit field of a property in a class from another class SystemVerilog SystemVerilog , class	1	525	January 9, 2023
The best way of using struct, class, and array SystemVerilog SystemVerilog , class , performance , simulation-performance	4	1072	October 24, 2022
Having instances of Both Child class and Parent class within a module SystemVerilog SystemVerilog , class , instantiation-vs-inheritance , chandle , extern-task-of-a-class	3	830	August 17, 2022
Unable to verify these errors SystemVerilog SystemVerilog , error , class , supernew	3	1199	August 15, 2022
Assign to interface input inside Class SystemVerilog SystemVerilog , class , interface , systemverilog-interface , assignment	3	588	June 14, 2022
Class handle copy SystemVerilog SystemVerilog , class , handle-svcopy-copy-memoryallocation-constructor	1	552	May 10, 2022
uvm_config_db#(T) labels uniqness within same scope UVM UVM , class , uvm-uvm_config_db , ParameterizedClass	2	558	April 23, 2022
Uvm_component is static UVM UVM , class , uvm_component , dynamic	5	1742	April 10, 2022
Why fatal error "Bad handle or reference" of this code SystemVerilog SystemVerilog , class , FATAL-ERROR , bad-handle-or-reference	1	762	June 21, 2021
If the default argument is initialized in the base_class function there is no error. But for the following explicit super.new the following error is obtained. Thanks in Advance SystemVerilog SystemVerilog , class , new-function	7	1977	December 31, 2019
Class static methods and static properies initialization and creation SystemVerilog SystemVerilog , class , static-method , static-property	5	3368	November 7, 2018
Class declaration within a class SystemVerilog SystemVerilog , class	1	1398	November 5, 2018
Can cast class type from another class? (Want to reduce redundant part) SystemVerilog SystemVerilog , class , handle	3	1303	July 25, 2018
Constraining an Object's Object's Variable SystemVerilog SystemVerilog , class , constraint	7	2039	July 9, 2018
UVM class hierarchy - type of relationship UVM UVM , class	4	3831	January 4, 2018
Trying debug a class object in env SystemVerilog SystemVerilog , class , Debug	2	1326	December 10, 2017
Writemem SystemVerilog SystemVerilog , class , object , program , writememh	7	11539	November 23, 2017
Partial override of a class OVM OVM , function , class , override , Inheritance	4	2219	October 23, 2017
Class and object in system verilog SystemVerilog SystemVerilog , class	1	1604	September 19, 2017
Factory objects and components are virtual? UVM UVM , class , SV , factory , virtual	1	1374	September 17, 2017
Why do we use classes in system verilog verification environment? SystemVerilog SystemVerilog , class	4	2671	June 8, 2017
Regarding Construct in Class SystemVerilog SystemVerilog , class , Cunstruct , new , taskfunction	5	1723	April 5, 2017
Classes SystemVerilog SystemVerilog , class	2	1576	January 3, 2017