Trying debug a class object in env

SystemVerilog
, ,
1

Hi
I am trying to debug a monitor class in environment class. Everything seems fine, but I get this error which I haven’t figure out why?

Error-[SE] Syntax error
Following verilog source has syntax error :
token ‘acc_monitor’ should be a valid type. Please declare it
virtual if it is an Interface.
“acc_env.sv”, 33: token is ‘;’
acc_monitor input_mon;
^
this is monitor class:

class acc_monitor;

acc_in_trans tx_in1;
mailbox #(acc_in_trans) mb2;
mailbox #(acc_in_trans) mb3;
virtual ac_if mon_if;

task run();
	forever begin
		tx_in1=new();
		@(posedge mon_if.clk iff !mon_if.rst)
		foreach(mon_if.in[i]) tx_in1.in[i]<=mon_if.in[i];

		tx_in1.rst<=mon_if.rst;
		
		mb2.put(tx_in1);
		mb3.put(tx_in1);
		
		//foreach(tx_in1.in[i])
		//	$display("in is %0d, sum is %0d, rst is %0d", tx_in1.in[i], tx_in1.sum, tx_in1.rst);
	end

endtask

endclass : acc_monitor

2

In reply to aliyar:

The error is token ‘acc_monitor’ should be a valid type. Please declare it. You can try to add acc_monitor typedef in acc_env.sv like below or make sure acc_monitor.sv is included before acc_env.sv


typedef class acc_monitor;
class acc_env;
...
3

In reply to Lina.Lin:

Thanks, it kind of worked but it’s not running. This is the whole code.