Uvm_component is static

UVM
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1

If class is a dynamic (gets created during runtime) datatype, how can uvm_component be static?

2

All SystemVerilog classes get constructed dynamically. You might have read somewhere that uvm_ component is effectively static after the build phase compared to other classes like uvm_sequence_item and other transactions. That just means the UVM component hierarchy is guaranteed to be stable for the entire test.

3

In reply to dave_59:

Dave ,

There’s a question I always had in my mind regarding quasi static components .


 //  Example ::  Within  Test's  build_phase 
    comp_h =  user_component :: type_id :: create ( "comp_h" , this ) ;
    comp_h =  null ;
    $display(" comp_h  is  %0s " , ( comp_h == null ) ? "null" : "non-null" ) ;

Since UVM is based on SystemVerilog , how is that that the null assignment is successful , but still the build_phase of user_component gets called ?

4

In reply to TC_2017:

Assigning null to a class variable does not delete the class object that was previously reference by the handle stored in the variable—it only deletes the reference to the object. Only when all references are removed can the object be considered “deleted”. The UVM provides no way to delete all reference to a uvm_component object, thus you cannot delete a uvm_compnent once it has been created.

When you construct a uvm_component, you pass the “this” handle as a second(parent) argument to the constructor method. The constructor appends a handle to the user_component to a list of children components in the parent component. The UVM uses the list of children to travers a top-down or depth-first traversal of the component hierarchy to execute the build_phase.

5

In reply to dave_59:
“
All SystemVerilog classes get constructed dynamically. You might have read somewhere that uvm_ component is effectively static after the build phase compared to other classes like uvm_sequence_item and other transactions. That just means the UVM component hierarchy is guaranteed to be stable for the entire test.“

Oh ok. The terminology is confusing. like when we say module is static, I understand it as it is available from compile time and then elaboration time to runtime. Hence saying uvm_component is static made it sound like it’s similar to module.
Sounds like the UVM build phase is different from the compile time (simulator) and the end of elaboration is different from the elaboration time?

6

In reply to natasv:

The people who wrote the AVM which became the OVM, which became the UVM “borrowed” the same terminology from Verilog simulation because it was effectively doing the same thing that a compiler does with modules, except with class objects