Uvm_component is static

UVM
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3

In reply to dave_59:

Dave ,

There’s a question I always had in my mind regarding quasi static components .


 //  Example ::  Within  Test's  build_phase 
    comp_h =  user_component :: type_id :: create ( "comp_h" , this ) ;
    comp_h =  null ;
    $display(" comp_h  is  %0s " , ( comp_h == null ) ? "null" : "non-null" ) ;

Since UVM is based on SystemVerilog , how is that that the null assignment is successful , but still the build_phase of user_component gets called ?