In reply to dave_59:
“
All SystemVerilog classes get constructed dynamically. You might have read somewhere that uvm_ component is effectively static after the build phase compared to other classes like uvm_sequence_item and other transactions. That just means the UVM component hierarchy is guaranteed to be stable for the entire test.“
Oh ok. The terminology is confusing. like when we say module is static, I understand it as it is available from compile time and then elaboration time to runtime. Hence saying uvm_component is static made it sound like it’s similar to module.
Sounds like the UVM build phase is different from the compile time (simulator) and the end of elaboration is different from the elaboration time?