Topics tagged module

Topic	Replies	Views	Activity
How to override severity report from UVM_ERROR to UVM_WARNING of a module UVM UVM , assertion , class , module , severity_overrride	2	1418	October 20, 2023
Set initial values of full signals of module SystemVerilog SystemVerilog , module , initialize	2	1032	July 6, 2023
Module cannot see defines defined in pkg, if this pkg is imported inside module. What is the reason for it? SystemVerilog SystemVerilog , Package , module , package-inside-module	6	933	November 10, 2022
How to avoid "Too few instance port connections" error? SystemVerilog SystemVerilog , module , instance , Build-in-module , too-few-port-connections , module-instantiation	1	2622	March 1, 2022
Module instantiation from within a for-gen block, value of input port is not updating SystemVerilog SystemVerilog , generate-block , module	4	1519	May 19, 2020
Which tools support module ports of type event? SystemVerilog SystemVerilog , module , event , port	2	870	October 31, 2019
Properties encapsulation OVM OVM , interface , module , encapsulation , Properties	2	1626	April 11, 2019
Reference model UVM SystemVerilog , UVM , module	7	11688	November 4, 2018
Reusable bind wrapper module SystemVerilog SystemVerilog , bind , parameter , module	0	1590	May 18, 2016
Converting a module to/using a module in OVM? OVM OVM , configuration , interface , module	4	2446	November 20, 2015