Reference model

UVM
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Hi Guys,

I have a questions about Reference model,

  • what does it mean?
  • how we build and implement it?
  • does it just like the design module? ,do we actually build a module that implement the spec.?

Please, refer me to articles or papers that explain it, or if there is an practical example.

Thank you in advance!.

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In reply to JH_Engineer:

A reference model is an executable specification - a golden model that predicts the correct results from the provided stimulus. How one implements a reference model is as varied the way specifications are written as well as each design.

Sometimes you are re-doing a design to fit on a smaller part. The reference model could be the previous design.

Many designs implement mathematical algorithms implemented in MatLAb or similar environments. They can generate C code to be used as a reference model.

This is a really big topic, so it’s difficult to explain in this forum.

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Thank you Dave.

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In reply to dave_59:

In reply to JH_Engineer:
A reference model is an executable specification - a golden model that predicts the correct results from the provided stimulus. How one implements a reference model is as varied the way specifications are written as well as each design.
Sometimes you are re-doing a design to fit on a smaller part. The reference model could be the previous design.
Many designs implement mathematical algorithms implemented in MatLAb or similar environments. They can generate C code to be used as a reference model.
This is a really big topic, so it’s difficult to explain in this forum.

Hi Dave,

In the industry most of the reference models are written in C.
Why is this c-based reference models ubiquitous?
Also, could we write them using SV? In this case we need not use DPIs.

Thank you,

Regards,
Muneeb

5

In reply to muneebullashariff:

Whether you see a lot of C reference models or not depends on which industry you are in. In many cases, C reference models are made available for use in other environments beside RTL verification, so why re-write these modules in SystemVerilog?

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In reply to dave_59:

In reply to muneebullashariff:
Whether you see a lot of C reference models or not depends on which industry you are in. In many cases, C reference models are made available for use in other environments beside RTL verification, so why re-write these modules in SystemVerilog?

Hi Dave,

Many thanks for your reply.

I have a requirement to develop the reference model for the processor. Moreover, the test-bench is developed using SV and UVM.

In which language should I code my reference model:
Using C or
Using SV

Furthermore, what is the best way to verify the reference model?

Regards,
Muneeb

7

In reply to muneebullashariff:

I have a requirement to develop the reference model for the processor. Moreover, the test-bench is developed using SV and UVM.
In which language should I code my reference model:
Using C or
Using SV
Furthermore, what is the best way to verify the reference model?

There is no common answer to your question. It depends on what you want to do with your reference model and where it will be used.
In a lot of cases you can reuse models written in C/C++ for use in system design. If you have such a model it should be already verified.
If you have an algorithmic design implementing certain algorithm you might use a Matlab model and connection Matlab to your UVM environment.
If you have a communication application the reference model might be quite simple because you have to store your data from the seperate streams in queues or tlm_fifos.
If you have no other application it depends which language is more familiar to oyu.

8

In reply to muneebullashariff:

In reply to dave_59:
Hi Dave,
Many thanks for your reply.
I have a requirement to develop the reference model for the processor. Moreover, the test-bench is developed using SV and UVM.
In which language should I code my reference model:
Using C or
Using SV
Furthermore, what is the best way to verify the reference model?
Regards,
Muneeb

Apart from what other members here have mentioned, keep also in mind that a reference model is expected to be a model against which you would conclude whether the DUT is correct or not.
Now, the features can themselves be temporal by nature.
If this is the case and any of the following is true then you are better off using SV for modelling:

  1. you want to verify the temporal behaviour of the DUT
  2. you have no other way to verify the temporal behaviour other than modelling it in reference model. For example, transactional level temporal checks can be easily done using assertions and should be the first choice. Deep sequential behaviour are hard to be captured using assertions. So, these will be mostly done in SV

Please also be aware that a reference model need not be monolithic. In fact, it is common to accomplish overall reference model behaviour using “sum of parts” approach. Meaning, many reference models can be combined to get the overall behaviour. So, you can have some in C++ domain and some in SV domain depending on all the above criteria mentioned above and by other members here.