In reply to dave_59:
In reply to muneebullashariff:
Whether you see a lot of C reference models or not depends on which industry you are in. In many cases, C reference models are made available for use in other environments beside RTL verification, so why re-write these modules in SystemVerilog?
Hi Dave,
Many thanks for your reply.
I have a requirement to develop the reference model for the processor. Moreover, the test-bench is developed using SV and UVM.
In which language should I code my reference model:
Using C or
Using SV
Furthermore, what is the best way to verify the reference model?
Regards,
Muneeb