Hi Guys, I have a questions about Reference model, what does it mean? how we build and implement it? does it just like the design module? ,do we actually build a module that implement the spec.? Please, refer me to articles or papers that explain it, or if there is an practical example. Thank y…

In reply to JH_Engineer : A reference model is an executable specification - a golden model that predicts the correct results from the provided stimulus. How one implements a reference model is as varied the way specifications are written as well as each design. Sometimes you are re-doing a design …

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Reference model

UVM

UVM, SystemVerilog, module

JaafarHassan August 29, 2018, 5:48am 3

Thank you Dave.

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