Hi Guys, I have a questions about Reference model, what does it mean? how we build and implement it? does it just like the design module? ,do we actually build a module that implement the spec.? Please, refer me to articles or papers that explain it, or if there is an practical example. Thank y…

In reply to JH_Engineer : A reference model is an executable specification - a golden model that predicts the correct results from the provided stimulus. How one implements a reference model is as varied the way specifications are written as well as each design. Sometimes you are re-doing a design …

In reply to dave_59 : In reply to JH_Engineer : A reference model is an executable specification - a golden model that predicts the correct results from the provided stimulus. How one implements a reference model is as varied the way specifications are written as well as each design. Sometimes you…

In reply to muneebullashariff : Whether you see a lot of C reference models or not depends on which industry you are in. In many cases, C reference models are made available for use in other environments beside RTL verification, so why re-write these modules in SystemVerilog?

In reply to dave_59 : In reply to muneebullashariff : Whether you see a lot of C reference models or not depends on which industry you are in. In many cases, C reference models are made available for use in other environments beside RTL verification, so why re-write these modules in SystemVerilog? …

In reply to muneebullashariff : I have a requirement to develop the reference model for the processor. Moreover, the test-bench is developed using SV and UVM. In which language should I code my reference model: Using C or Using SV Furthermore, what is the best way to verify the reference model? …

In reply to muneebullashariff : In reply to dave_59 : Hi Dave, Many thanks for your reply. I have a requirement to develop the reference model for the processor. Moreover, the test-bench is developed using SV and UVM. In which language should I code my reference model: Using C or Using SV Fur…

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Reference model

UVM

SystemVerilog, UVM, module

JaafarHassan August 29, 2018, 5:48am 3

Thank you Dave.

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