Set initial values of full signals of module

SystemVerilog
, ,
1

I’m struggling to find the way for initializing value set of signals in module

This is the thing that I want to do :

  1. I have initial values of full signals of module

  2. I want to set those initial value when I call module

    For example,

      1)  there is a module named IO_MODULE (which is already designed)


     module IO_MODULE (A,B,C ,,,)
       input A;
       input B;              
       input C;
           ...

     endmodule


 2)  And I also have initial value set of full signals of this IO_MODULE such as

     A = 1'b1 , B= 1'b0, C= 1'b1  ...


 3)   I wonder, is there a way to set those initial value of signals when I call 'IO_MODULE' ( ->  IO_MODULE IO_MODULE_0 (.A(a) , .B(b) ,,,,   )
2

In reply to ben@SystemVerilog.us:

It seems like you are asking about how to write a testbench:

https://fpgatutorial.com/how-to-write-a-basic-verilog-testbench/

http://www.testbench.in/TS_04_TESTBENCH.html

3

In reply to dave_59:

Maybe what you mean is changing the initial defaulted values of the RTL module to a different value from a top level. You can use the force release.



module m;
  int a; 
  initial begin 
    a=3; 
    #20 a=16'h34;
  end 
endmodule 

module top; 
 //int b=7;
  m m1(); 
  initial begin 
    $dumpfile("dump.vcd"); $dumpvars;
    force m1.a = 32'h75;
    #10;
    release m1.a;
    #100 $finish;
  end
endmodule

Ben Cohen
Ben@systemverilog.us
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