Just hit a weird issue yesterday. I was partitioning some monitor/error code into sub-modules. One of the signals was an error named event that signaled that an error had occurred. I added this as an output port of my new submodule but Cadence Xcelium say this is illegal and I found a support page that stated they don’t support this. There are many workarounds but it’s a headache. So, I was wondering if Synopsys VCS or Mentor Questa support this. Should be ok according to 1800-2017.
In reply to dhrogoff:
This forum does not discuss tools,
It addresses design and verification languages, application and use questions on the languages, but definitely not tools. Tool questions are answered by vendors at their support sites.
This approach maintains the integrity and neutrality of this forum.
Ben
I agree with you that any data type is legal as a port declaration according to the IEEE 1800-2017 LRM. There are restrictions on the kind of signals connected to a port instance.