Verification Academy

port

Topic		Replies	Views	Activity
Is it possible to use "packed array of enum logics" as I/O port of a module? SystemVerilog SystemVerilog , typedef , enum , port , packedarray		2	478	June 19, 2023
Which tools support module ports of type event? SystemVerilog SystemVerilog , module , event , port		2	871	October 31, 2019