Is it possible to use "packed array of enum logics" as I/O port of a module?

SystemVerilog
, , , ,
1

I have a shared enum logic typedef used to store FSM state type of module_A. I want to use the state information of multiple instances of module_A, in module_B. Is it possible to use packed array of typedef enum logics as I/O port? Is it synthesizable? If not, what could you suggest me to use?



package my_package;
    typedef enum logic [1:0] {
        STATE_0,
        STATE_1,
        STATE_2,
        STATE_3
    } module_a_state_t;
endpackage


module module_A (
    output my_package::module_a_state_t state_o
);
    // Module body:

    my_package::module_a_state_t    current_state, next_state;

    // FSM goes here
    // ...

endmodule


module module_B #(
    .NUMBER_OF_MODULE_A_INSTANCES
)(
    input [NUMBER_OF_MODULE_A_INSTANCES-1:0] my_package::module_a_state_t   multiple_states_i  // Is this possible? Is it synthesizable?
);
    // Module body
    // ...
    
endmodule

I know that I can make it without using typedef enum logic, such as below. But I want to have an I/O port as generic as possible. In this case being generic means if want to extend the state cases, changing the enum logic width in the package should be enough.


input logic [NUMBER_OF_MODULE_A_INSTANCES:0][1:0]  // I don't want to use this.
2

In reply to veli:

What you wrote is legal and should be synthesizable (I would double-check your tools before getting too far along).

Note that you might want to import the package in the module header to avoid having to repeat the package references.

module module_A import my_package::*; (
    output module_a_state_t state_o
);
  // Module body:
 
    module_a_state_t    current_state, next_state;
 
    // FSM goes here
    // ...
       next_state = STATE_0;
 
 
endmodule
3

In reply to dave_59:

Thank you Dave. I will give it a try in my tool, and let the forum know about it.