Is it possible to use "packed array of enum logics" as I/O port of a module?

SystemVerilog
, , , ,
2

In reply to veli:

What you wrote is legal and should be synthesizable (I would double-check your tools before getting too far along).

Note that you might want to import the package in the module header to avoid having to repeat the package references.

module module_A import my_package::*; (
    output module_a_state_t state_o
);
  // Module body:
 
    module_a_state_t    current_state, next_state;
 
    // FSM goes here
    // ...
       next_state = STATE_0;
 
 
endmodule