Topics tagged enum

Topic	Replies	Views	Activity
Assign value to an enum from command line UVM SystemVerilog , UVM , Command-Line-Processing , enum	2	152	August 30, 2024
How to display/print type casted enum as string without using variable SystemVerilog SystemVerilog , enum , typecasting , typecast	2	219	July 31, 2024
How to assign value to the function from different class with different enum SystemVerilog SystemVerilog , typedef , enum	5	494	October 11, 2023
Is it possible to use "packed array of enum logics" as I/O port of a module? SystemVerilog SystemVerilog , typedef , enum , port , packedarray	2	452	June 19, 2023
Anonymous(unnamed) enum type from DUT to interface SystemVerilog SystemVerilog , enum , 0sim-time	3	552	June 14, 2023
Assigning 1st element of enum as non-zero and accessing it SystemVerilog SystemVerilog , enum	3	703	April 6, 2023
Enum of same names SystemVerilog SystemVerilog , System-Verilog , enum	3	1267	February 13, 2023
Coverpoint bins with enum excluded Coverage SystemVerilog , Coverage , coverpoint , enum	1	895	November 8, 2022
Enumeration type element ranges SystemVerilog SystemVerilog , enum	4	1401	June 1, 2022
Enum value override from test UVM UVM , enum	7	1480	April 2, 2022
SystemVerilog typedef enum SystemVerilog SystemVerilog , enum , systemverilog-enum-classes-constraints , variable-in-typedef	1	1661	July 8, 2021
How can I use hex value into enum? SystemVerilog SystemVerilog , enum	8	4521	February 3, 2021
Enumarated data types SystemVerilog SystemVerilog , enum	3	846	January 5, 2021
Defining array's range according to enumerated type attributes SystemVerilog SystemVerilog , typedef , enum , attributes , Vivado , synplify_premier	2	1047	May 24, 2020
$value$plusargs not setting the desired value SystemVerilog SystemVerilog , typedef , enum , valueplusargs	6	12334	May 11, 2020
Indexing an array through an enum datatype SystemVerilog SystemVerilog , enum , systemverilog-Arrays , FPGA , systemverilog-enum-classes-constraints	1	3936	April 1, 2020
"Invalid random variable in index expression for constraint" SystemVerilog SystemVerilog , constraint , randomization , enum , constraint-array	2	1426	December 10, 2019
Macro defined with undefined typedef enums SystemVerilog SystemVerilog , enum , define	1	1238	October 1, 2019
How to register associative array of enum with enum key in UVM factory? UVM UVM , associative-array , enum , field-macros	2	3469	February 20, 2019
How to randomize bit array to have one bit high at a time SystemVerilog SystemVerilog , enum , constraints	3	3695	September 16, 2018
Enumerated type with common member SystemVerilog SystemVerilog , enum	3	1145	May 24, 2018
Constraining a union of enums SystemVerilog SystemVerilog , structure-and-union , enum , constraints	3	3207	May 18, 2018
Fail to cast of enum SystemVerilog SystemVerilog , enum , random	2	4336	August 3, 2017
Can I use a dynamic array to set a distribution? SystemVerilog SystemVerilog , constraint , dist , enum	1	2581	August 14, 2015