Enumeration type element ranges

SystemVerilog
,
1

From LRM, I should be able to define an enumerated range with the syntax:

typedef enum { add, sub[5] } e_t;

This syntax should create the enums: add, sub0, sub1, sub2, sub3, sub4.

However, I get an error when I try to use a parameter instead of the “5”:



parameter bit [7:0] SIZE = 5;
typedef enum { add, sub[SIZE] } e_t;

Error: Enumeration range must evaluate to a positive integer.

Am I missing something?

2

In reply to a_stod:

All of commercial simulators in EDAPlayGround got an error.
There is no comments in LRM but I think SIZE can not change the value at elaborate and simulation stage.
Parameter value can change at elaborate stage by using “-defparam” or other option of simulators.

It works if it set the value by using `define.


`define SIZE 5
typedef enum { add, sub[`SIZE] } e_t;

I hope Dave will explain cause of the error in detail.

3

In reply to a_stod:

The syntax for enum ranges only allows for literal constants, not parameters. This is because the enum identifier names get created at parse time, not at a later stage when parameters can get overridden at elaboration stage.

4

In reply to dave_59:

Hi Dave,

While I understand the reasoning of your explanation from the LRM there is no mention about not allowing parameters, maybe it is implied, but it is not clear for the general audience like myself :)

-R

5

In reply to rgarcia07:

-R,

The BNF is the ultimate reference for what syntax can or cannot be accepted. And this is right at the beginning of the section on enums.

enum_name_declaration ::=
    enum_identifier [ [ integral_number [ : integral_number ] ] ] [ = constant_expression ]

integral_number ::=
    decimal_number
  | octal_number
  | binary_number
  | hex_number

A constant_expression can include a parameter as an operand, but a number is a literal value.