Anonymous(unnamed) enum type from DUT to interface

SystemVerilog
, ,
1

Hi folks,

I get one question on unnamed enum type from DUT assigning to interface variable.
At time 0, the interface variable - nxt_st contains 0 somehow. Can someone help me understand it?

If interface always wants to skip the time 0 change on nxt_st without modifying module - my_fsm, how to fix it in a reasonable way?


`define ANONYMOUS_INT

module my_fsm(
                input clk,
                input rst_n
                );

`ifdef ANONYMOUS_INT
  enum {                    //0: 'h0, 'h40
`else
  enum logic [7:0] {        //0: 'h40
`endif
         S0 = 'h40,
         S1 = 'h0, //non-initial state
         S2 = 'h1,
         S3 = 'h2
         } st, nxt_st;

   always @(posedge clk or negedge rst_n) begin
      if(~rst_n) begin
         st <= S0;
      end else begin
         st <= nxt_st;
      end
   end

   always @(*) begin
      nxt_st = st;
   end

   // always @(nxt_st) begin
   //    $display("%0t: %s",$realtime, nxt_st.name());
   // end
   
endmodule


interface my_if(input clk, rst_n);
   logic [7:0] nxt_st;

   assign nxt_st = tb.dut.nxt_st;

   always @(nxt_st) begin
      $display("%0t: 'h%0h",$realtime, nxt_st);
   end
endinterface


module tb;

   bit clk, rst_n;

   my_fsm dut(.clk(clk), .rst_n(rst_n));
   my_if if0(.clk(clk), .rst_n(rst_n));

   always #1 clk = ~clk;

   initial begin
      #2 rst_n = 1;
      #10 $finish();
   end
   
   initial begin
     $dumpfile("dump.vcd");
     $dumpvars(0, tb);
   end
   
endmodule

Thanks ~

2

In reply to mlsxdx:

This has nothing to do with being an anonymous type. The implicit data type of any enum is a 2-state int. The default initial value of an enum is the default initial value of its data type, which is 0 because that default type is an int. .

3

In reply to dave_59:

In reply to mlsxdx:
This has nothing to do with being an anonymous type. The implicit data type of any enum is a 2-state int. The default initial value of an enum is the default initial value of its data type, which is 0 because that default type is an int. .

I see. Is there any way to skip time 0 nxt_st changes trigger always, especially if 0 is defined a non-initial state.


   always @(nxt_st) begin
      $display("%0t: 'h%0h",$realtime, nxt_st);
      // The unname enum 0 will trigger the logic below, how can I filter out the sim time 0 here?
      if(nxt_st != 'h40) begin
        //statement
      end
   end
4

In reply to mlsxdx:

In reply to dave_59:
I see. Is there any way to skip time 0 nxt_st changes trigger always, especially if 0 is defined a non-initial state.


always @(nxt_st or rst_n) begin
$display("%0t: 'h%0h",$realtime, nxt_st);
// The unname enum 0 will trigger the logic below, how can I filter out the sim time 0 here?
if(!rst_n) begin 
//pass
end else if(nxt_st != 'h40) begin
//statement
end
end

Sorry for the confusion. I have difficulty to figure out how to skip the simulation time 0 nxt_st change which triggers @(nxt_st). Now I found that by using rst_n, it can skip time 0.