Topics tagged constraint

Topic	Replies	Views	Activity
Column sum constraint for an 2D array SystemVerilog constraint , constraint-randomization , 2D-array-SystemVerilog-randomization	5	61	March 8, 2025
Valid Data Filter SystemVerilog SystemVerilog , System-Verilog , constraint , constraint-randomization , Verilog , constraints , systemverilog-constraint	2	72	February 16, 2025
System Verilog Clock Generation SystemVerilog SystemVerilog , constraint , clock	1	94	December 5, 2024
Adding a function in constraint doesn't work UVM constraint , constraint-randomization	2	95	November 18, 2024
SV Constraint Question - Keeping 1s together SystemVerilog SystemVerilog , constraint	3	627	August 31, 2024
Want to generate array of one hot numbers using system Verilog constraints SystemVerilog constraint , constraint-randomization	2	447	April 30, 2024
Write a constraint that assigns data to any address sequence that follows an arithmetic progression (ex: 1,5,9,13,17.. so a[1]=30, a[5]=30, a[9]=30 and so on)) SystemVerilog constraint , constraint-randomization , systemverilog-constraint	5	415	April 21, 2024
Write a constraint for polindrome (say 32 bit)? SystemVerilog SystemVerilog , constraint	15	7015	April 7, 2024
Is there any way to set a global solve...before? SystemVerilog SystemVerilog , constraint , solve-before	1	227	April 3, 2024
SV Constraint :: Address must be aligned to the size of the transfer SystemVerilog SystemVerilog , constraint , constraint-randomization	7	748	March 14, 2024
SystemVerilog - Constraint display issue SystemVerilog SystemVerilog , constraint , constraint-randomization	1	438	February 5, 2024
Limit the number of transitions in a 32 bit number SystemVerilog SystemVerilog , constraint , constraint-randomization	3	502	January 30, 2024
What is missing makes constraints results incorrect? SystemVerilog constraint	5	207	December 28, 2023
Constraint solver issue, while this constraint sometimes results in errors? SystemVerilog SystemVerilog , constraint , constraint-randomization	2	1055	November 30, 2023
Constraint solver error using the config object of subsequence in the nested sequence and subsequence that inherited the base sequence UVM UVM , constraint , nested-sequence , subsequence , base-sequence	4	626	October 6, 2023
Divide operator in Constraints SystemVerilog SystemVerilog , constraint	3	725	June 30, 2023
Debugging a complex constraint SystemVerilog SystemVerilog , constraint	2	798	January 6, 2023
Compare unpacked array in constraint SystemVerilog SystemVerilog , constraint	1	509	December 13, 2022
Object handles and randomization SystemVerilog SystemVerilog , constraint , constraint-randomization	11	7004	September 15, 2022
Constraint existence of value into an array SystemVerilog SystemVerilog , constraint , randomization , array-methods , arrays	6	4278	August 24, 2022
Random constraints SystemVerilog SystemVerilog , constraint , random	1	598	July 25, 2022
Soft constraints SystemVerilog SystemVerilog , constraint	1	982	November 19, 2021
Randomize with conditional based on non-class signal SystemVerilog SystemVerilog , constraint , Randomize	2	954	October 8, 2021
How to control randomization of each item in an array acc. to parameter SystemVerilog SystemVerilog , constraint , randomization	2	975	April 12, 2021
Using String Type within a Constraint Expression SystemVerilog SystemVerilog , constraint	2	1394	March 13, 2021
Constrain the number of occurrences in an array SystemVerilog SystemVerilog , constraint , array-randomization	9	3883	November 8, 2020
Why associative array will not randomized, if its index is user defined? SystemVerilog SystemVerilog , constraint , randomization , associative-array , randomization-associative-array	1	1043	September 14, 2020
Static function usage in constraints SystemVerilog SystemVerilog , constraint , Static-function	2	1182	August 25, 2020
How constraint solver resolves conflicting constraints in dist? SystemVerilog SystemVerilog , randomization-constraints , constraint , constraint-dist	3	3133	August 1, 2020
Constraint for 32 bit addr to be different than prev addr by 2 bits SystemVerilog SystemVerilog , constraint	13	5212	July 31, 2020

Column sum constraint for an 2D array

SystemVerilog

constraint , constraint-randomization , 2D-array-SystemVerilog-randomization

5

61

March 8, 2025

Valid Data Filter

SystemVerilog

SystemVerilog , System-Verilog , constraint , constraint-randomization , Verilog , constraints , systemverilog-constraint

2

72

February 16, 2025

System Verilog Clock Generation

SystemVerilog

SystemVerilog , constraint , clock

1

94

December 5, 2024

Adding a function in constraint doesn't work

UVM

constraint , constraint-randomization

2

95

November 18, 2024

SV Constraint Question - Keeping 1s together

SystemVerilog

SystemVerilog , constraint

3

627

August 31, 2024

Want to generate array of one hot numbers using system Verilog constraints

SystemVerilog

constraint , constraint-randomization

2

447

April 30, 2024

Write a constraint that assigns data to any address sequence that follows an arithmetic progression (ex: 1,5,9,13,17.. so a[1]=30, a[5]=30, a[9]=30 and so on))

SystemVerilog

constraint , constraint-randomization , systemverilog-constraint

5

415

April 21, 2024

Write a constraint for polindrome (say 32 bit)?

SystemVerilog

SystemVerilog , constraint

15

7015

April 7, 2024

Is there any way to set a global solve...before?

SystemVerilog

SystemVerilog , constraint , solve-before

1

227

April 3, 2024

SV Constraint :: Address must be aligned to the size of the transfer

SystemVerilog

SystemVerilog , constraint , constraint-randomization

7

748

March 14, 2024

SystemVerilog - Constraint display issue

SystemVerilog

SystemVerilog , constraint , constraint-randomization

1

438

February 5, 2024

Limit the number of transitions in a 32 bit number

SystemVerilog

SystemVerilog , constraint , constraint-randomization

3

502

January 30, 2024

What is missing makes constraints results incorrect?

SystemVerilog

constraint

5

207

December 28, 2023

Constraint solver issue, while this constraint sometimes results in errors?

SystemVerilog

SystemVerilog , constraint , constraint-randomization

2

1055

November 30, 2023

Constraint solver error using the config object of subsequence in the nested sequence and subsequence that inherited the base sequence

UVM

UVM , constraint , nested-sequence , subsequence , base-sequence

4

626

October 6, 2023

Divide operator in Constraints

SystemVerilog

SystemVerilog , constraint

3

725

June 30, 2023

Debugging a complex constraint

SystemVerilog

SystemVerilog , constraint

2

798

January 6, 2023

Compare unpacked array in constraint

SystemVerilog

SystemVerilog , constraint

1

509

December 13, 2022

Object handles and randomization

SystemVerilog

SystemVerilog , constraint , constraint-randomization

11

7004

September 15, 2022

Constraint existence of value into an array

SystemVerilog

SystemVerilog , constraint , randomization , array-methods , arrays

6

4278

August 24, 2022

Random constraints

SystemVerilog

SystemVerilog , constraint , random

1

598

July 25, 2022

Soft constraints

SystemVerilog

SystemVerilog , constraint

1

982

November 19, 2021

Randomize with conditional based on non-class signal

SystemVerilog

SystemVerilog , constraint , Randomize

2

954

October 8, 2021

How to control randomization of each item in an array acc. to parameter

SystemVerilog

SystemVerilog , constraint , randomization

2

975

April 12, 2021

Using String Type within a Constraint Expression

SystemVerilog

SystemVerilog , constraint

2

1394

March 13, 2021

Constrain the number of occurrences in an array

SystemVerilog

SystemVerilog , constraint , array-randomization

9

3883

November 8, 2020

Why associative array will not randomized, if its index is user defined?

SystemVerilog

SystemVerilog , constraint , randomization , associative-array , randomization-associative-array

1

1043

September 14, 2020

Static function usage in constraints

SystemVerilog

SystemVerilog , constraint , Static-function

2

1182

August 25, 2020

How constraint solver resolves conflicting constraints in dist?

SystemVerilog

SystemVerilog , randomization-constraints , constraint , constraint-dist

3

3133

August 1, 2020

Constraint for 32 bit addr to be different than prev addr by 2 bits

SystemVerilog

SystemVerilog , constraint

13

5212

July 31, 2020