Soft constraints

SystemVerilog
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1

I have a bit of a doubt on the soft constraints.

This is what LRM mentions about the soft constraint:

a constraint expression defined as soft designates a constraint that is to be satisfied unless contradicted by another constraint—either by a hard constraint or by a soft constraint with higher priority.

So, in the following code, is this a contradiction:

constraint deflt { soft length < 5 ; }
constraint new_const { soft length < 10 ; }

In the above example, would the soft constraint be overridden and only the new_const considered or both the constraints would be considered?
Similarly, what happens when the constraints are interchanged like below:

constraint deflt { soft length < 10 ; }
constraint new_const { soft length < 5 ; }
2

In reply to shatrish:

These constraints do not contradict each other they both can be satisfied with numbers less than 5. Other the other hand if you had

constraint deflt { soft length < 5 ; }
constraint new_const { soft length > 10 ; }

Both these constraints cannot be satisfied together. The last constraint “new_const” has priority.